Datasheet MCP6051, MCP6052, MCP6054 (Microchip) - 5

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MCP6051/2/4 1.3 Test Circuits
C The circuit used for most DC and AC tests is shown in F 6.8 pF Figure 1-1. This circuit can independently set VCM and VOUT; see Equation 1-1. Note that VCM is not the circuit’s common mode voltage ((V R P + VM)/2), and that G RF V 100 kΩ OST includes VOS plus the effects (on the input offset 100 kΩ error, V V V OST) of temperature, CMRR, PSRR and AOL. P DD/2 VDD
EQUATION 1-1:
VIN+ C C B1 B2 G = R ⁄ R DM F G
MCP605X
100 nF 1 µF V = (V + V ⁄ 2) ⁄ 2 CM P DD V = V – V V OST IN – IN+ IN– V = (V ⁄ 2) + (V – V ) + V (1 + G ) OUT DD P M OST DM V V M OUT Where: R R C G RF L L 100 kΩ 100 kΩ 10 kΩ 60 pF GDM = Differential Mode Gain (V/V) VCM = Op Amp’s Common Mode (V) C Input Voltage F VL 6.8 pF VOST = Op Amp’s Total Input Offset (mV) Voltage
FIGURE 1-1:
AC and DC Test Circuit for Most Specifications. © 2010 Microchip Technology Inc. DS22182B-page 5 Document Outline MCP6051/2/4 Applications Design Aids Typical Application Description Package Types 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings † 1.2 Specifications TABLE 1-1: DC electrical specifications TABLE 1-2: AC Electrical Specifications TABLE 1-3: temperature specifications 1.3 Test Circuits EQUATION 1-1: FIGURE 1-1: AC and DC Test Circuit for Most Specifications. Notes: 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage with VDD = 3.0V. FIGURE 2-2: Input Offset Voltage Drift with VDD = 3.0V and TA £ +85°C. FIGURE 2-3: Input Offset Voltage Drift with VDD = 3.0V and TA ³ +85°C. FIGURE 2-4: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 6.0V. FIGURE 2-5: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 3.0V. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 1.8V. FIGURE 2-7: Input Offset Voltage vs. Output Voltage. FIGURE 2-8: Input Offset Voltage vs. Power Supply Voltage. FIGURE 2-9: Input Noise Voltage Density vs. Frequency. FIGURE 2-10: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-11: CMRR, PSRR vs. Frequency. FIGURE 2-12: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-13: Common Mode Input Voltage Range Limit vs. Ambient Temperature. FIGURE 2-14: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-15: Input Bias Current vs. Common Mode Input Voltage. FIGURE 2-16: Quiescent Current vs Ambient Temperature with VCM = 0.9VDD. FIGURE 2-17: Quiescent Current vs. Power Supply Voltage with VCM = 0.9VDD. FIGURE 2-18: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-19: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-20: DC Open-Loop Gain vs. Output Voltage Headroom. FIGURE 2-21: Channel-to-Channel Separation vs. Frequency (MCP6052/4 only). FIGURE 2-22: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage. FIGURE 2-23: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-24: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-25: Ouput Short Circuit Current vs. Power Supply Voltage. FIGURE 2-26: Output Voltage Swing vs. Frequency. FIGURE 2-27: Ratio of Output Voltage Headroom to Output Current vs. Output Current. FIGURE 2-28: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-29: Slew Rate vs. Ambient Temperature. FIGURE 2-30: Small Signal Non-Inverting Pulse Response. FIGURE 2-31: Small Signal Inverting Pulse Response. FIGURE 2-32: Large Signal Non-Inverting Pulse Response. FIGURE 2-33: Large Signal Inverting Pulse Response. FIGURE 2-34: The MCP6051/2/4 Shows No Phase Reversal. FIGURE 2-35: Closed Loop Output Impedance vs. Frequency. FIGURE 2-36: Measured Input Current vs. Input Voltage (below VSS). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins 3.4 Exposed Thermal Pad (EP) Notes: 4.0 Application Information 4.1 Rail-to-Rail Input 4.1.1 Phase Reversal 4.1.2 Input Voltage Limits FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.1.3 Input Current Limits FIGURE 4-3: Protecting the Analog Inputs. 4.1.4 Normal Operation 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-4: Output Resistor, RISO Stabilizes Large Capacitive Loads. FIGURE 4-5: Recommended RISO Values for Capacitive Loads. 4.4 Supply Bypass 4.5 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.6 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 1. Non-inverting Gain and Unity-Gain Buffer: a) Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b) Connect the guard ring to the inverting input pin (VIN–). This biases the guard ring to the common mode input voltage. 2. Inverting Gain and Transimpedance Gain Amplifiers (convert current to voltage, such as photo detectors): a) Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b) Connect the inverting pin (VIN–) to the input with a wire that does not touch the PCB surface. 4.7 Application Circuits 4.7.1 Gyrator FIGURE 4-8: Gyrator. 4.7.2 Instrumentation Amplifier FIGURE 4-9: Two Op Amp Instrumentation Amplifier. 4.7.3 Precision Comparator FIGURE 4-10: Precision, Non-inverting Comparator. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Microchip Advanced Part Selector (MAPS) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes Notes: 6.0 Packaging Information Features 6.1 Package Marking Information 30 µA, High Precision Op Amps Appendix A: Revision History Revision B (December 2010) 1. Added new SOT-23-5 package type for MCP6051 device. 2. Corrected Figures 2-13, 2-22, 2-23, 2-24 and 2-28 in Section 2.0 “Typical Performance Curves”. 3. Modified Table 3-1 to show the pin column for MCP6051, SOT-23-5 package. 4. Updated Section 4.1.2 “Input Voltage Limits”. 5. Added Section 4.1.3 “Input Current Limits”. 6. Added new document item in Section 5.5 “Application Notes”. 7. Updated the package markings information and drawings. 8. Updated the Product Identification System page. Revision A (May 2009) Notes: a) MCP6051T-E/OT: Tape and Reel, 5LD SOT-23 package b) MCP6051-E/SN: 8LD SOIC package c) MCP6051T-E/SN: Tape and Reel, 8LD SOIC package d) MCP6051T-E/MNY: Tape and Reel, 8LD 2x3 TDFN package a) MCP6052-E/SN: 8LD SOIC package b) MCP6052T-E/SN: Tape and Reel, 8LD SOIC package c) MCP6052T-E/MNY: Tape and Reel 8LD 2x3 TDFN package a) MCP6054-E/SL: 14LD SOIC package b) MCP6054T-E/SL: Tape and Reel, 14LD SOIC package c) MCP6054-E/ST: 14LD TSSOP package d) MCP6054T-E/ST: Tape and Reel, 14LD TSSOP package Notes: Worldwide Sales and Service Trademarks Worldwide Sales