Datasheet ATmega161, ATmega161L (Atmel) - 2
| Manufacturer | Atmel |
| Description | 8-bit AVR Microcontroller with 16K Bytes of In-System Programmable Flash |
| Pages / Page | 159 / 2 — Pin Configuration. ATmega161(L) |
| File Format / Size | PDF / 1.8 Mb |
| Document Language | English |
Pin Configuration. ATmega161(L)
Model Line for this Datasheet
Text Version of Document
Pin Configuration
PDIP (OC0/T0) PB0 1 40 VCC (OC2/T1) PB1 2 39 PA0 (AD0) (RXD1/AIN0) PB2 3 38 PA1 (AD1) (TXD1/AIN1) PB3 4 37 PA2 (AD2) (SS) PB4 5 36 PA3 (AD3) (MOSI) PB5 6 35 PA4 (AD4) (MISO) PB6 7 34 PA5 (AD5) (SCK) PB7 8 33 PA6 (AD6) RESET 9 32 PA7 (AD7) (RXD0) PD0 10 31 PE0 (ICP/INT2) (TXD0) PD1 11 30 PE1 (ALE) (INT0) PD2 12 29 PE2 (OC1B) (INT1) PD3 13 28 PC7 (A15) (TOSC1) PD4 14 27 PC6 (A14) (OC1A/TOSC2) PD5 15 26 PC5 (A13) (WR) PD6 16 25 PC4 (A12) (RD) PD7 17 24 PC3 (A11) XTAL2 18 23 PC2 (A10) XTAL1 19 22 PC1 (A9) GND 20 21 PC0 (A8) TQFP A0 (AD0) A1 (AD1) A2 (AD2) PB4 (SS) PB3 (TXD1/AIN1) PB2 (RXD1/AIN0) PB1 (OC2/T1) PB0 (OC0/T0) NC* VCC P P P PA3 (AD3) 44 43 42 41 40 39 38 37 36 35 34 (MOSI) PB5 1 33 PA4 (AD4) (MISO) PB6 2 32 PA5 (AD5) (SCK) PB7 3 31 PA6 (AD6) RESET 4 30 PA7 (AD7) (RXD0) PD0 5 29 PE0 (ICP/INT2) NC* 6 28 NC* (TXD0) PD1 7 27 PE1 (ALE) (INT0) PD2 8 26 PE2 (OC1B) (INT1) PD3 9 25 PC7 (A15) (TOSC1) PD4 10 24 PC6 (A14) (OCIA/TOSC2) PD5 11 23 PC5 (A13) 12 13 14 15 16 17 18 19 20 21 22 * NC = Do not connect AL2 AL1 (Can be used in future devices) GND NC* XT XT (WR) PD6 (RD) PD7 (A8) PC0 (A9) PC1 (A10) PC2 (A11) PC3 (A12) PC4
2 ATmega161(L)
1228D–AVR–02/07 Document Outline Features Disclaimer Pin Configuration Description Block Diagram Pin Descriptions VCC GND Port A (PA7..PA0) Port B (PB7..PB0) Port C (PC7..PC0) Port D (PD7..PD0) Port E (PE2..PE0) RESET XTAL1 XTAL2 Crystal Oscillator Architectural Overview The General Purpose Register File The X-register, Y-register and Z-register ALU - Arithmetic Logic Unit Self-programmable Flash Program Memory EEPROM Data Memory SRAM Data Memory Program and Data Addressing Modes Register Direct, Single Register Rd Register Direct, Two Registers Rd and Rr I/O Direct Data Direct Data Indirect with Displacement Data Indirect Data Indirect with Pre- decrement Data Indirect with Post- increment Constant Addressing Using the LPM Instruction Indirect Program Addressing, IJMP and ICALL Relative Program Addressing, RJMP and RCALL Direct Program Addressing, JMP and CALL Memory Access Times and Instruction Execution Timing l/O Memory Status Register - SREG Stack Pointer - SP Reset and Interrupt Handling Reset Sources Power-on Reset External Reset Watchdog Reset MCU Status Register - MCUSR Interrupt Handling Interrupt Response Time General Interrupt Mask Register - GIMSK General Interrupt Flag Register - GIFR Timer/Counter Interrupt Mask Register - TIMSK Timer/Counter Interrupt Flag Register - TIFR External Interrupts MCU Control Register - MCUCR Extended MCU Control Register - EMCUCR Sleep Modes Idle Mode Power-down Mode Power-save Mode Timer/Counters Timer/Counter Prescalers Special Function IO Register - SFIOR 8-bit Timer/Counters T/C0 and T/C2 Timer/Counter0 Control Register - TCCR0 Timer/Counter2 Control Register - TCCR2 Timer Counter0 - TCNT0 Timer/Counter2 - TCNT2 Timer/Counter0 Output Compare Register - OCR0 Timer/Counter2 Output Compare Register - OCR2 Timer/Counters 0 and 2 in PWM Mode PWM Modes (Up/Down and Overflow) Asynchronous Status Register - ASSR Asynchronous Operation of Timer/Counter2 Timer/Counter1 Timer/Counter1 Control Register A - TCCR1A Timer/Counter1 Control Register B - TCCR1B Timer/Counter1 Register - TCNT1H AND TCNT1L Timer/Counter1 Output Compare Register - OCR1AH AND OCR1AL Timer/Counter1 Output Compare Register - OCR1BH AND OCR1BL Timer/Counter1 Input Capture Register - ICR1H AND ICR1L Timer/Counter1 in PWM Mode Watchdog Timer Watchdog Timer Control Register - WDTCR EEPROM Read/Write Access EEPROM Address Register - EEARH and EEARL EEPROM Data Register - EEDR EEPROM Control Register - EECR Prevent EEPROM Corruption Serial Peripheral Interface - SPI SS Pin Functionality Data Modes SPI Control Register - SPCR SPI Status Register - SPSR SPI Data Register - SPDR UARTs Data Transmission Data Reception Multi-processor Communication Mode UART Control UART0 I/O Data Register - UDR0 UART1 I/O Data Register - UDR1 UART0 Control and Status Registers - UCSR0A UART1 Control and Status Registers - UCSR1A UART0 Control and Status Registers - UCSR0B UART1 Control and Status Registers - UCSR1B Baud Rate Generator UART0 and UART1 High Byte Baud Rate Register UBRRHI UART0 Baud Rate Register Low Byte - UBRR0 UART1 Baud Rate Register Low Byte - UBRR1 Double-speed Transmission The Baud Rate Generator in Double UART Speed Mode Analog Comparator Analog Comparator Control and Status Register - ACSR Internal Voltage Reference Voltage Reference Enable Signals and Start- up Time Interface to External Memory MCU Control Register - MCUCR Extended MCU Control Register - EMCUCR Using the External Memory Interface I/O Ports Port A Port A Data Register - PORTA Port A Data Direction Register - DDRA Port A Input Pins Address - PINA Port A as General Digital I/O Port A Schematics Port B Port B Data Register - PORTB Port B Data Direction Register - DDRB Port B Input Pins Address - PINB Port B as General Digital I/O Alternate Functions of Port B Port B Schematics Port C Port C Data Register - PORTC Port C Data Direction Register - DDRC Port C Input Pins Address - PINC Port C as General Digital I/O Port C Schematics Port D Port D Data Register - PORTD Port D Data Direction Register - DDRD Port D Input Pins Address - PIND Port D as General Digital I/O Alternate Functions of Port D Port D Schematics Port E Port E Data Register - PORTE Port E Data Direction Register - DDRE Port E Input Pins Address - PINE Port E as General Digital I/O Alternate Functions of Port E Port E Schematics Memory Programming Boot Loader Support Entering the Boot Loader Program Capabilities of the Boot Loader Self-programming the Flash Setting the Boot Loader Lock bits by SPM Performing Page Erase by SPM Fill the Temporary Buffer Perform a Page Write Addressing the FLASH during Self-programming Store Program Memory Control Register - SPMCR EEPROM Write Prevents Writing to SPMCR Reading the Fuse and Lock bits from Software Program Memory Lock bits Fuse bits Signature Bytes Programming the Flash and EEPROM Parallel Programming Signal Names Enter Programming Mode Chip Erase Programming the Flash Programming the EEPROM Reading the Flash Reading the EEPROM Programming the Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes Parallel Programming Characteristics Serial Downloading Serial Programming Algorithm Data Polling Flash Data Polling EEPROM Serial Programming Characteristics Electrical Characteristics Absolute Maximum Ratings* DC Characteristics External Clock Drive Waveforms External Data Memory Timing Typical Characteristics Register Summary Instruction Set Summary (Continued) Ordering Information Packaging Information 44A 40P6 Errata ATmega161 Rev. E Data Sheet Change Log for ATmega161 Changes from Rev. 1228C-08 /02 to Rev. 1228D-02/07 Changes from Rev. 1228B-09/01 to Rev. 1228C-08/02 Table of Contents
PDIP (OC0/T0) PB0 1 40 VCC (OC2/T1) PB1 2 39 PA0 (AD0) (RXD1/AIN0) PB2 3 38 PA1 (AD1) (TXD1/AIN1) PB3 4 37 PA2 (AD2) (SS) PB4 5 36 PA3 (AD3) (MOSI) PB5 6 35 PA4 (AD4) (MISO) PB6 7 34 PA5 (AD5) (SCK) PB7 8 33 PA6 (AD6) RESET 9 32 PA7 (AD7) (RXD0) PD0 10 31 PE0 (ICP/INT2) (TXD0) PD1 11 30 PE1 (ALE) (INT0) PD2 12 29 PE2 (OC1B) (INT1) PD3 13 28 PC7 (A15) (TOSC1) PD4 14 27 PC6 (A14) (OC1A/TOSC2) PD5 15 26 PC5 (A13) (WR) PD6 16 25 PC4 (A12) (RD) PD7 17 24 PC3 (A11) XTAL2 18 23 PC2 (A10) XTAL1 19 22 PC1 (A9) GND 20 21 PC0 (A8) TQFP A0 (AD0) A1 (AD1) A2 (AD2) PB4 (SS) PB3 (TXD1/AIN1) PB2 (RXD1/AIN0) PB1 (OC2/T1) PB0 (OC0/T0) NC* VCC P P P PA3 (AD3) 44 43 42 41 40 39 38 37 36 35 34 (MOSI) PB5 1 33 PA4 (AD4) (MISO) PB6 2 32 PA5 (AD5) (SCK) PB7 3 31 PA6 (AD6) RESET 4 30 PA7 (AD7) (RXD0) PD0 5 29 PE0 (ICP/INT2) NC* 6 28 NC* (TXD0) PD1 7 27 PE1 (ALE) (INT0) PD2 8 26 PE2 (OC1B) (INT1) PD3 9 25 PC7 (A15) (TOSC1) PD4 10 24 PC6 (A14) (OCIA/TOSC2) PD5 11 23 PC5 (A13) 12 13 14 15 16 17 18 19 20 21 22 * NC = Do not connect AL2 AL1 (Can be used in future devices) GND NC* XT XT (WR) PD6 (RD) PD7 (A8) PC0 (A9) PC1 (A10) PC2 (A11) PC3 (A12) PC4
2 ATmega161(L)
1228D–AVR–02/07 Document Outline Features Disclaimer Pin Configuration Description Block Diagram Pin Descriptions VCC GND Port A (PA7..PA0) Port B (PB7..PB0) Port C (PC7..PC0) Port D (PD7..PD0) Port E (PE2..PE0) RESET XTAL1 XTAL2 Crystal Oscillator Architectural Overview The General Purpose Register File The X-register, Y-register and Z-register ALU - Arithmetic Logic Unit Self-programmable Flash Program Memory EEPROM Data Memory SRAM Data Memory Program and Data Addressing Modes Register Direct, Single Register Rd Register Direct, Two Registers Rd and Rr I/O Direct Data Direct Data Indirect with Displacement Data Indirect Data Indirect with Pre- decrement Data Indirect with Post- increment Constant Addressing Using the LPM Instruction Indirect Program Addressing, IJMP and ICALL Relative Program Addressing, RJMP and RCALL Direct Program Addressing, JMP and CALL Memory Access Times and Instruction Execution Timing l/O Memory Status Register - SREG Stack Pointer - SP Reset and Interrupt Handling Reset Sources Power-on Reset External Reset Watchdog Reset MCU Status Register - MCUSR Interrupt Handling Interrupt Response Time General Interrupt Mask Register - GIMSK General Interrupt Flag Register - GIFR Timer/Counter Interrupt Mask Register - TIMSK Timer/Counter Interrupt Flag Register - TIFR External Interrupts MCU Control Register - MCUCR Extended MCU Control Register - EMCUCR Sleep Modes Idle Mode Power-down Mode Power-save Mode Timer/Counters Timer/Counter Prescalers Special Function IO Register - SFIOR 8-bit Timer/Counters T/C0 and T/C2 Timer/Counter0 Control Register - TCCR0 Timer/Counter2 Control Register - TCCR2 Timer Counter0 - TCNT0 Timer/Counter2 - TCNT2 Timer/Counter0 Output Compare Register - OCR0 Timer/Counter2 Output Compare Register - OCR2 Timer/Counters 0 and 2 in PWM Mode PWM Modes (Up/Down and Overflow) Asynchronous Status Register - ASSR Asynchronous Operation of Timer/Counter2 Timer/Counter1 Timer/Counter1 Control Register A - TCCR1A Timer/Counter1 Control Register B - TCCR1B Timer/Counter1 Register - TCNT1H AND TCNT1L Timer/Counter1 Output Compare Register - OCR1AH AND OCR1AL Timer/Counter1 Output Compare Register - OCR1BH AND OCR1BL Timer/Counter1 Input Capture Register - ICR1H AND ICR1L Timer/Counter1 in PWM Mode Watchdog Timer Watchdog Timer Control Register - WDTCR EEPROM Read/Write Access EEPROM Address Register - EEARH and EEARL EEPROM Data Register - EEDR EEPROM Control Register - EECR Prevent EEPROM Corruption Serial Peripheral Interface - SPI SS Pin Functionality Data Modes SPI Control Register - SPCR SPI Status Register - SPSR SPI Data Register - SPDR UARTs Data Transmission Data Reception Multi-processor Communication Mode UART Control UART0 I/O Data Register - UDR0 UART1 I/O Data Register - UDR1 UART0 Control and Status Registers - UCSR0A UART1 Control and Status Registers - UCSR1A UART0 Control and Status Registers - UCSR0B UART1 Control and Status Registers - UCSR1B Baud Rate Generator UART0 and UART1 High Byte Baud Rate Register UBRRHI UART0 Baud Rate Register Low Byte - UBRR0 UART1 Baud Rate Register Low Byte - UBRR1 Double-speed Transmission The Baud Rate Generator in Double UART Speed Mode Analog Comparator Analog Comparator Control and Status Register - ACSR Internal Voltage Reference Voltage Reference Enable Signals and Start- up Time Interface to External Memory MCU Control Register - MCUCR Extended MCU Control Register - EMCUCR Using the External Memory Interface I/O Ports Port A Port A Data Register - PORTA Port A Data Direction Register - DDRA Port A Input Pins Address - PINA Port A as General Digital I/O Port A Schematics Port B Port B Data Register - PORTB Port B Data Direction Register - DDRB Port B Input Pins Address - PINB Port B as General Digital I/O Alternate Functions of Port B Port B Schematics Port C Port C Data Register - PORTC Port C Data Direction Register - DDRC Port C Input Pins Address - PINC Port C as General Digital I/O Port C Schematics Port D Port D Data Register - PORTD Port D Data Direction Register - DDRD Port D Input Pins Address - PIND Port D as General Digital I/O Alternate Functions of Port D Port D Schematics Port E Port E Data Register - PORTE Port E Data Direction Register - DDRE Port E Input Pins Address - PINE Port E as General Digital I/O Alternate Functions of Port E Port E Schematics Memory Programming Boot Loader Support Entering the Boot Loader Program Capabilities of the Boot Loader Self-programming the Flash Setting the Boot Loader Lock bits by SPM Performing Page Erase by SPM Fill the Temporary Buffer Perform a Page Write Addressing the FLASH during Self-programming Store Program Memory Control Register - SPMCR EEPROM Write Prevents Writing to SPMCR Reading the Fuse and Lock bits from Software Program Memory Lock bits Fuse bits Signature Bytes Programming the Flash and EEPROM Parallel Programming Signal Names Enter Programming Mode Chip Erase Programming the Flash Programming the EEPROM Reading the Flash Reading the EEPROM Programming the Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes Parallel Programming Characteristics Serial Downloading Serial Programming Algorithm Data Polling Flash Data Polling EEPROM Serial Programming Characteristics Electrical Characteristics Absolute Maximum Ratings* DC Characteristics External Clock Drive Waveforms External Data Memory Timing Typical Characteristics Register Summary Instruction Set Summary (Continued) Ordering Information Packaging Information 44A 40P6 Errata ATmega161 Rev. E Data Sheet Change Log for ATmega161 Changes from Rev. 1228C-08 /02 to Rev. 1228D-02/07 Changes from Rev. 1228B-09/01 to Rev. 1228C-08/02 Table of Contents
