Datasheet AD8368 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | 800 MHz, Linear-in-dB VGA with AGC Detector |
| Pages / Page | 20 / 4 — AD8368. Data Sheet. Table 2. Parameter. Min. Typ. Max. Unit. Conditions |
| Revision | C |
| File Format / Size | PDF / 743 Kb |
| Document Language | English |
AD8368. Data Sheet. Table 2. Parameter. Min. Typ. Max. Unit. Conditions
Model Line for this Datasheet
Text Version of Document
link to page 14
AD8368 Data Sheet
VS = 5 V, TA = 25°C, system impedance Z0 = 50 Ω, VMODE = 5 V, RF input = 140 MHz, unless otherwise noted.
Table 2. Parameter Min Typ Max Unit Conditions
SQUARE LAW DETECTOR (DETI, DETO) Output Setpoint −11 dBm OUTP connected to DETI DETI DC Bias Level to ICOM VS/2 V DETI Impedance 710 Ω 0.6 pF DETO Output Range1 0.1 VS/2 V AGC Step Response 30 µs For −6 dB input power step (CDETO = 1 nF) MODE CONTROL INTERFACE (MODE) MODE Threshold 3.5 V MODE Input Bias Current 50 µA POWER INTERFACE (VPSI, VPSO) Supply Voltage 4.5 5 5.5 V Total Supply Current 60 mA ENBL high Disable Current 2 mA ENBL low ENABLE INTERFACE (ENBL) Enable Threshold 2.5 V Enable Response Time 1.5 µs Time delay following off-to-on transition until output reaches 90% of final value 3 µs Time delay following on-to-off transition until supply current is less than 5 mA ENBL Input Bias Current 150 µA VENBL = 5 V 1 Refer to AGC Operation section. Rev. C | Page 4 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT DESCRIPTION INPUT ATTENUATOR AND INTERPOLATOR FIXED-GAIN STAGE AND OUTPUT BUFFER OUTPUT OFFSET CORRECTION INPUT AND OUTPUT IMPEDANCES GAIN CONTROL INTERFACE APPLICATIONS INFORMATION VGA OPERATION AGC OPERATION STABILITY AND LAYOUT CONSIDERATIONS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE
AD8368 Data Sheet
VS = 5 V, TA = 25°C, system impedance Z0 = 50 Ω, VMODE = 5 V, RF input = 140 MHz, unless otherwise noted.
Table 2. Parameter Min Typ Max Unit Conditions
SQUARE LAW DETECTOR (DETI, DETO) Output Setpoint −11 dBm OUTP connected to DETI DETI DC Bias Level to ICOM VS/2 V DETI Impedance 710 Ω 0.6 pF DETO Output Range1 0.1 VS/2 V AGC Step Response 30 µs For −6 dB input power step (CDETO = 1 nF) MODE CONTROL INTERFACE (MODE) MODE Threshold 3.5 V MODE Input Bias Current 50 µA POWER INTERFACE (VPSI, VPSO) Supply Voltage 4.5 5 5.5 V Total Supply Current 60 mA ENBL high Disable Current 2 mA ENBL low ENABLE INTERFACE (ENBL) Enable Threshold 2.5 V Enable Response Time 1.5 µs Time delay following off-to-on transition until output reaches 90% of final value 3 µs Time delay following on-to-off transition until supply current is less than 5 mA ENBL Input Bias Current 150 µA VENBL = 5 V 1 Refer to AGC Operation section. Rev. C | Page 4 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT DESCRIPTION INPUT ATTENUATOR AND INTERPOLATOR FIXED-GAIN STAGE AND OUTPUT BUFFER OUTPUT OFFSET CORRECTION INPUT AND OUTPUT IMPEDANCES GAIN CONTROL INTERFACE APPLICATIONS INFORMATION VGA OPERATION AGC OPERATION STABILITY AND LAYOUT CONSIDERATIONS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE
