Datasheet LTC3728L-1 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Dual, 550kHz, 2-Phase Synchronous Regulator |
| Pages / Page | 32 / 10 — OPERATION (Refer to Functional Diagram). Main Control Loop. Frequency … |
| File Format / Size | PDF / 487 Kb |
| Document Language | English |
OPERATION (Refer to Functional Diagram). Main Control Loop. Frequency Synchronization. Constant Frequency Operation
Model Line for this Datasheet
Text Version of Document
LTC3728L-1
OPERATION (Refer to Functional Diagram) Main Control Loop
by temporarily forcing continuous PWM operation on both controllers; and 2) to select between two modes The LTC3728L-1 is a constant frequency, current mode of low current operation. When the FCB pin voltage is step-down controller with two channels operating 180 below 0.8V, the controller forces continuous PWM cur- degrees out of phase. During normal operation, each top rent mode operation. In this mode, the top and bottom MOSFET is turned on when the clock for that channel sets MOSFETs are alternately turned on to maintain the output the RS latch, and turned off when the main current com- voltage independent of direction of inductor current. parator, I1, resets the RS latch. The peak inductor current When the FCB pin is below V at which I INTVCC – 2V but greater 1 resets the RS latch is controlled by the voltage than 0.8V, the controller enters Burst Mode operation. on the ITH pin, which is the output of each error amplifi er Burst Mode operation sets a minimum output current EA. The VOSENSE pin receives the voltage feedback signal, level before inhibiting the top switch and turns off the which is compared to the internal reference voltage by the synchronous MOSFET(s) when the inductor current goes EA. When the load current increases, it causes a slight negative. This combination of requirements will, at low decrease in VOSENSE relative to the 0.8V reference, which currents, force the I in turn causes the I TH pin below a voltage threshold that TH voltage to increase until the average will temporarily inhibit turn-on of both output MOSFETs inductor current matches the new load current. After the until the output voltage drops. There is 60mV of hyster- top MOSFET has turned off, the bottom MOSFET is turned esis in the burst comparator B tied to the I on until either the inductor current starts to reverse, as TH pin. This hysteresis produces output signals to the MOSFETs that indicated by current comparator I2, or the beginning of turn them on for several cycles, followed by a variable the next cycle. “sleep” interval depending upon the load current. The The top MOSFET drivers are biased from fl oating bootstrap resultant output voltage ripple is held to a very small capacitor CB, which normally is recharged during each off value by having the hysteretic comparator after the error cycle through an external diode when the top MOSFET amplifi er gain block. turns off. As VIN decreases to a voltage close to VOUT, the loop may enter dropout and attempt to turn on the top
Frequency Synchronization
MOSFET continuously. The dropout detector detects this The phase-locked loop allows the internal oscillator to and forces the top MOSFET off for about 400ns every tenth be synchronized to an external source via the PLLIN pin. cycle to allow CB to recharge. The output of the phase detector at the PLLFLTR pin is The main control loop is shut down by pulling the RUN/SS also the DC frequency control input of the oscillator that pin low. Releasing RUN/SS allows an internal 1.2μA cur- operates over a 260kHz to 550kHz range corresponding rent source to charge soft-start capacitor CSS. When CSS to a DC voltage input from 0V to 2.4V. When locked, the reaches 1.5V, the main control loop is enabled with the ITH PLL aligns the turn on of the top MOSFET to the rising voltage clamped at approximately 30% of its maximum edge of the synchronizing signal. When PLLIN is left value. As CSS continues to charge, the ITH pin voltage is open, the PLLFLTR pin goes low, forcing the oscillator to gradually released allowing normal, full-current operation. minimum frequency. When both RUN/SS1 and RUN/SS2 are low, all controller functions are shut down, including the 5V regulator.
Constant Frequency Operation
When the FCB pin is tied to INTV
Low Current Operation
CC, Burst Mode opera- tion is disabled and the forced minimum output current The FCB pin is a multifunction pin providing two func- requirement is removed. This provides constant frequency, tions: 1) to provide regulation for a secondary winding discontinuous current (preventing reverse inductor cur- rent) operation over the widest possible output current range. This constant frequency operation is not as effi cient 3728l1fc 10
OPERATION (Refer to Functional Diagram) Main Control Loop
by temporarily forcing continuous PWM operation on both controllers; and 2) to select between two modes The LTC3728L-1 is a constant frequency, current mode of low current operation. When the FCB pin voltage is step-down controller with two channels operating 180 below 0.8V, the controller forces continuous PWM cur- degrees out of phase. During normal operation, each top rent mode operation. In this mode, the top and bottom MOSFET is turned on when the clock for that channel sets MOSFETs are alternately turned on to maintain the output the RS latch, and turned off when the main current com- voltage independent of direction of inductor current. parator, I1, resets the RS latch. The peak inductor current When the FCB pin is below V at which I INTVCC – 2V but greater 1 resets the RS latch is controlled by the voltage than 0.8V, the controller enters Burst Mode operation. on the ITH pin, which is the output of each error amplifi er Burst Mode operation sets a minimum output current EA. The VOSENSE pin receives the voltage feedback signal, level before inhibiting the top switch and turns off the which is compared to the internal reference voltage by the synchronous MOSFET(s) when the inductor current goes EA. When the load current increases, it causes a slight negative. This combination of requirements will, at low decrease in VOSENSE relative to the 0.8V reference, which currents, force the I in turn causes the I TH pin below a voltage threshold that TH voltage to increase until the average will temporarily inhibit turn-on of both output MOSFETs inductor current matches the new load current. After the until the output voltage drops. There is 60mV of hyster- top MOSFET has turned off, the bottom MOSFET is turned esis in the burst comparator B tied to the I on until either the inductor current starts to reverse, as TH pin. This hysteresis produces output signals to the MOSFETs that indicated by current comparator I2, or the beginning of turn them on for several cycles, followed by a variable the next cycle. “sleep” interval depending upon the load current. The The top MOSFET drivers are biased from fl oating bootstrap resultant output voltage ripple is held to a very small capacitor CB, which normally is recharged during each off value by having the hysteretic comparator after the error cycle through an external diode when the top MOSFET amplifi er gain block. turns off. As VIN decreases to a voltage close to VOUT, the loop may enter dropout and attempt to turn on the top
Frequency Synchronization
MOSFET continuously. The dropout detector detects this The phase-locked loop allows the internal oscillator to and forces the top MOSFET off for about 400ns every tenth be synchronized to an external source via the PLLIN pin. cycle to allow CB to recharge. The output of the phase detector at the PLLFLTR pin is The main control loop is shut down by pulling the RUN/SS also the DC frequency control input of the oscillator that pin low. Releasing RUN/SS allows an internal 1.2μA cur- operates over a 260kHz to 550kHz range corresponding rent source to charge soft-start capacitor CSS. When CSS to a DC voltage input from 0V to 2.4V. When locked, the reaches 1.5V, the main control loop is enabled with the ITH PLL aligns the turn on of the top MOSFET to the rising voltage clamped at approximately 30% of its maximum edge of the synchronizing signal. When PLLIN is left value. As CSS continues to charge, the ITH pin voltage is open, the PLLFLTR pin goes low, forcing the oscillator to gradually released allowing normal, full-current operation. minimum frequency. When both RUN/SS1 and RUN/SS2 are low, all controller functions are shut down, including the 5V regulator.
Constant Frequency Operation
When the FCB pin is tied to INTV
Low Current Operation
CC, Burst Mode opera- tion is disabled and the forced minimum output current The FCB pin is a multifunction pin providing two func- requirement is removed. This provides constant frequency, tions: 1) to provide regulation for a secondary winding discontinuous current (preventing reverse inductor cur- rent) operation over the widest possible output current range. This constant frequency operation is not as effi cient 3728l1fc 10
