Datasheet ADP7118 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 20 V, 200 mA, Low Noise, CMOS LDO Linear Regulator |
| Pages / Page | 24 / 5 — Data Sheet. ADP7118. ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating. … |
| Revision | E |
| File Format / Size | PDF / 1.5 Mb |
| Document Language | English |
Data Sheet. ADP7118. ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating. THERMAL DATA. THERMAL RESISTANCE
Model Line for this Datasheet
- ADP7118ACPZN-R7 ADP7118ACPZN1.8-R7 ADP7118ACPZN2.5-R7 ADP7118ACPZN3.3-R7 ADP7118ACPZN5.0-R7 ADP7118ARDZ ADP7118ARDZ-1.8 ADP7118ARDZ-1.8-R7 ADP7118ARDZ-2.5 ADP7118ARDZ-2.5-R7 ADP7118ARDZ-3.3 ADP7118ARDZ-3.3-R7 ADP7118ARDZ-5.0 ADP7118ARDZ-5.0-R7 ADP7118ARDZ-R7 ADP7118AUJZ-1.8-R7 ADP7118AUJZ-2.5-R7 ADP7118AUJZ-3.3-R7 ADP7118AUJZ-4.5-R7 ADP7118AUJZ-5.0-R7 ADP7118AUJZ-R2 ADP7118AUJZ-R7 ADP7118WAUJZ-5.0-R7
Text Version of Document
Data Sheet ADP7118 ABSOLUTE MAXIMUM RATINGS Table 3.
θJA of the package is based on modeling and calculation using a 4-layer board. The θ
Parameter Rating
JA is highly dependent on the application and board layout. In applications where high maximum power VIN to GND –0.3 V to +24 V dissipation exists, close attention to thermal board design is VOUT to GND –0.3 V to VIN required. The value of θ EN to GND –0.3 V to +24 V JA may vary, depending on PCB material, layout, and environmental conditions. The specified values of SENSE/ADJ to GND –0.3 V to +6 V θ SS to GND –0.3 V to VIN or +6 V JA are based on a 4-layer, 4 inches × 3 inches circuit board. See (whichever is less) JESD51-7 and JESD51-9 for detailed information on the board Storage Temperature Range –65°C to +150°C construction. Junction Temperature (T Ψ J) 150°C JB is the junction-to-board thermal characterization parameter Operating Ambient Temperature (T –40°C to +125°C with units of °C/W. The ΨJB of the package is based on modeling A) Range and calculation using a 4-layer board. The JESD51-12, Guidelines Soldering Conditions JEDEC J-STD-020 for Reporting and Using Electronic Package Thermal Information, states that thermal characterization parameters are not the same Stresses at or above those listed under Absolute Maximum as thermal resistances. ΨJB measures the component power flowing Ratings may cause permanent damage to the product. This is a through multiple thermal paths rather than a single path as in stress rating only; functional operation of the product at these thermal resistance (θJB). Therefore, ΨJB thermal paths include or any other conditions above those indicated in the operational convection from the top of the package as well as radiation from section of this specification is not implied. Operation beyond the package, factors that make ΨJB more useful in real-world the maximum operating conditions for extended periods may applications. Maximum TJ is calculated from the board affect product reliability. temperature (TB) and PD using the formula
THERMAL DATA
TJ = TB + (PD × ΨJB) (2) Absolute maximum ratings apply individually only, not in See JESD51-8 and JESD51-12 for more detailed information combination. The ADP7118 can be damaged when the junction about ΨJB. temperature limits are exceeded. Monitoring ambient temperature does not guarantee that T
THERMAL RESISTANCE
J is within the specified temperature limits. In applications with high power dissipation and poor θJA, θJC, and ΨJB are specified for the worst-case conditions, that thermal resistance, the maximum ambient temperature may is, a device soldered in a circuit board for surface-mount packages. have to be derated.
Table 4. Thermal Resistance
In applications with moderate power dissipation and low
Package Type θJA θJC ΨJB Unit
printed circuit board (PCB) thermal resistance, the maximum 6-Lead LFCSP 72.1 42.3 47.1 °C/W ambient temperature can exceed the maximum limit as long as 8-Lead SOIC 52.7 41.5 32.7 °C/W the junction temperature is within specification limits. The 5-Lead TSOT 170 N/A1 43 °C/W junction temperature of the device is dependent on the ambient temperature, the power dissipation (PD) of the device, and the 1 N/A means not applicable. junction-to-ambient thermal resistance of the package (θJA).
ESD CAUTION
Maximum TJ is calculated from the TA and PD using the formula TJ = TA + (PD × θJA) (1) Rev. E | Page 5 of 24 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUITS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS INPUT AND OUTPUT CAPACITANCE, RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties PROGRAMABLE PRECISION ENABLE SOFT START NOISE REDUCTION OF THE ADP7118 IN ADJUSTABLE MODE EFFECT OF NOISE REDUCTION ON START-UP TIME CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION THERMAL CONSIDERATIONS PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS
θJA of the package is based on modeling and calculation using a 4-layer board. The θ
Parameter Rating
JA is highly dependent on the application and board layout. In applications where high maximum power VIN to GND –0.3 V to +24 V dissipation exists, close attention to thermal board design is VOUT to GND –0.3 V to VIN required. The value of θ EN to GND –0.3 V to +24 V JA may vary, depending on PCB material, layout, and environmental conditions. The specified values of SENSE/ADJ to GND –0.3 V to +6 V θ SS to GND –0.3 V to VIN or +6 V JA are based on a 4-layer, 4 inches × 3 inches circuit board. See (whichever is less) JESD51-7 and JESD51-9 for detailed information on the board Storage Temperature Range –65°C to +150°C construction. Junction Temperature (T Ψ J) 150°C JB is the junction-to-board thermal characterization parameter Operating Ambient Temperature (T –40°C to +125°C with units of °C/W. The ΨJB of the package is based on modeling A) Range and calculation using a 4-layer board. The JESD51-12, Guidelines Soldering Conditions JEDEC J-STD-020 for Reporting and Using Electronic Package Thermal Information, states that thermal characterization parameters are not the same Stresses at or above those listed under Absolute Maximum as thermal resistances. ΨJB measures the component power flowing Ratings may cause permanent damage to the product. This is a through multiple thermal paths rather than a single path as in stress rating only; functional operation of the product at these thermal resistance (θJB). Therefore, ΨJB thermal paths include or any other conditions above those indicated in the operational convection from the top of the package as well as radiation from section of this specification is not implied. Operation beyond the package, factors that make ΨJB more useful in real-world the maximum operating conditions for extended periods may applications. Maximum TJ is calculated from the board affect product reliability. temperature (TB) and PD using the formula
THERMAL DATA
TJ = TB + (PD × ΨJB) (2) Absolute maximum ratings apply individually only, not in See JESD51-8 and JESD51-12 for more detailed information combination. The ADP7118 can be damaged when the junction about ΨJB. temperature limits are exceeded. Monitoring ambient temperature does not guarantee that T
THERMAL RESISTANCE
J is within the specified temperature limits. In applications with high power dissipation and poor θJA, θJC, and ΨJB are specified for the worst-case conditions, that thermal resistance, the maximum ambient temperature may is, a device soldered in a circuit board for surface-mount packages. have to be derated.
Table 4. Thermal Resistance
In applications with moderate power dissipation and low
Package Type θJA θJC ΨJB Unit
printed circuit board (PCB) thermal resistance, the maximum 6-Lead LFCSP 72.1 42.3 47.1 °C/W ambient temperature can exceed the maximum limit as long as 8-Lead SOIC 52.7 41.5 32.7 °C/W the junction temperature is within specification limits. The 5-Lead TSOT 170 N/A1 43 °C/W junction temperature of the device is dependent on the ambient temperature, the power dissipation (PD) of the device, and the 1 N/A means not applicable. junction-to-ambient thermal resistance of the package (θJA).
ESD CAUTION
Maximum TJ is calculated from the TA and PD using the formula TJ = TA + (PD × θJA) (1) Rev. E | Page 5 of 24 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUITS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS INPUT AND OUTPUT CAPACITANCE, RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties PROGRAMABLE PRECISION ENABLE SOFT START NOISE REDUCTION OF THE ADP7118 IN ADJUSTABLE MODE EFFECT OF NOISE REDUCTION ON START-UP TIME CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION THERMAL CONSIDERATIONS PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS
