Datasheet AD8021 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | Low Noise, High Speed Amplifier for 16-Bit Systems |
| Pages / Page | 28 / 4 — AD8021. AD8021AR/AD8021ARM. Parameter Conditions. Min. Typ. Max. Unit. … |
| Revision | F |
| File Format / Size | PDF / 436 Kb |
| Document Language | English |
AD8021. AD8021AR/AD8021ARM. Parameter Conditions. Min. Typ. Max. Unit. Table 2. AD8021AR/AD8021ARM
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AD8021 AD8021AR/AD8021ARM Parameter Conditions Min Typ Max Unit
Disabled Leakage Current LOGIC REFERENCE = 0.4 V 30 μA DISABLE = 0.4 V 33 μA POWER SUPPLY Operating Range ±2.25 ±5 ±12.0 V Quiescent Current Output enabled 7.0 7.7 mA Output disabled 1.3 1.6 mA +Power Supply Rejection Ratio VCC = 4 V to 6 V, VEE = −5 V −86 −95 dB −Power Supply Rejection Ratio VCC = 5 V, VEE = −6 V to −4 V −86 −95 dB VS = ±12 V, @ TA = 25°C, RL = 1 kΩ, gain = +2, unless otherwise noted.
Table 2. AD8021AR/AD8021ARM Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth G = +1, CC = 10 pF, VO = 0.05 V p-p 520 560 MHz G = +2, CC = 7 pF, VO = 0.05 V p-p 175 220 MHz G = +5, CC = 2 pF, VO = 0.05 V p-p 170 200 MHz G = +10, CC = 0 pF, VO = 0.05 V p-p 125 165 MHz Slew Rate, 1 V Step G = +1, CC = 10 pF 105 130 V/μs G = +2, CC = 7 pF 140 170 V/μs G = +5, CC = 2 pF 265 340 V/μs G = +10, CC = 0 pF 400 460 V/μs Settling Time to 0.01% VO = 1 V step, RL = 500 Ω 21 ns Overload Recovery (50%) ±6 V input step, G = +2 90 ns DISTORTION/NOISE PERFORMANCE f = 1 MHz HD2 VO = 2 V p-p −95 dBc HD3 VO = 2 V p-p −116 dBc f = 5 MHz HD2 VO = 2 V p-p −71 dBc HD3 VO = 2 V p-p −83 dBc Input Voltage Noise f = 50 kHz 2.1 2.6 nV/√Hz Input Current Noise f = 50 kHz 2.1 pA/√Hz Differential Gain Error NTSC, RL = 150 Ω 0.03 % Differential Phase Error NTSC, RL = 150 Ω 0.04 Degrees DC PERFORMANCE Input Offset Voltage 0.4 1.0 mV Input Offset Voltage Drift TMIN to TMAX 0.2 μV/°C Input Bias Current +Input or −input 8 11.3 μA Input Bias Current Drift 10 nA/°C Input Offset Current 0.1 0.5 ±μA Open-Loop Gain 84 88 dB INPUT CHARACTERISTICS Input Resistance 10 MΩ Common-Mode Input Capacitance 1 pF Input Common-Mode Voltage Range −11.1 to +11.6 V Common-Mode Rejection Ratio VCM = ±10 V −86 −96 dB Rev. F | Page 4 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION CONNECTION DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS APPLICATIONS USING THE DISABLE FEATURE THEORY OF OPERATION PCB LAYOUT CONSIDERATIONS DRIVING 16-BIT ADCs DIFFERENTIAL DRIVER USING THE AD8021 IN ACTIVE FILTERS DRIVING CAPACITIVE LOADS OUTLINE DIMENSIONS ORDERING GUIDE
Disabled Leakage Current LOGIC REFERENCE = 0.4 V 30 μA DISABLE = 0.4 V 33 μA POWER SUPPLY Operating Range ±2.25 ±5 ±12.0 V Quiescent Current Output enabled 7.0 7.7 mA Output disabled 1.3 1.6 mA +Power Supply Rejection Ratio VCC = 4 V to 6 V, VEE = −5 V −86 −95 dB −Power Supply Rejection Ratio VCC = 5 V, VEE = −6 V to −4 V −86 −95 dB VS = ±12 V, @ TA = 25°C, RL = 1 kΩ, gain = +2, unless otherwise noted.
Table 2. AD8021AR/AD8021ARM Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth G = +1, CC = 10 pF, VO = 0.05 V p-p 520 560 MHz G = +2, CC = 7 pF, VO = 0.05 V p-p 175 220 MHz G = +5, CC = 2 pF, VO = 0.05 V p-p 170 200 MHz G = +10, CC = 0 pF, VO = 0.05 V p-p 125 165 MHz Slew Rate, 1 V Step G = +1, CC = 10 pF 105 130 V/μs G = +2, CC = 7 pF 140 170 V/μs G = +5, CC = 2 pF 265 340 V/μs G = +10, CC = 0 pF 400 460 V/μs Settling Time to 0.01% VO = 1 V step, RL = 500 Ω 21 ns Overload Recovery (50%) ±6 V input step, G = +2 90 ns DISTORTION/NOISE PERFORMANCE f = 1 MHz HD2 VO = 2 V p-p −95 dBc HD3 VO = 2 V p-p −116 dBc f = 5 MHz HD2 VO = 2 V p-p −71 dBc HD3 VO = 2 V p-p −83 dBc Input Voltage Noise f = 50 kHz 2.1 2.6 nV/√Hz Input Current Noise f = 50 kHz 2.1 pA/√Hz Differential Gain Error NTSC, RL = 150 Ω 0.03 % Differential Phase Error NTSC, RL = 150 Ω 0.04 Degrees DC PERFORMANCE Input Offset Voltage 0.4 1.0 mV Input Offset Voltage Drift TMIN to TMAX 0.2 μV/°C Input Bias Current +Input or −input 8 11.3 μA Input Bias Current Drift 10 nA/°C Input Offset Current 0.1 0.5 ±μA Open-Loop Gain 84 88 dB INPUT CHARACTERISTICS Input Resistance 10 MΩ Common-Mode Input Capacitance 1 pF Input Common-Mode Voltage Range −11.1 to +11.6 V Common-Mode Rejection Ratio VCM = ±10 V −86 −96 dB Rev. F | Page 4 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION CONNECTION DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS APPLICATIONS USING THE DISABLE FEATURE THEORY OF OPERATION PCB LAYOUT CONSIDERATIONS DRIVING 16-BIT ADCs DIFFERENTIAL DRIVER USING THE AD8021 IN ACTIVE FILTERS DRIVING CAPACITIVE LOADS OUTLINE DIMENSIONS ORDERING GUIDE
