Datasheet ACT 1 (Actel)

link to page 4

ACT™ 1 Series FPGAs
F e a t u r e s
A security fuse may be programmed to disable all further • 5V and 3.3V Families fully compatible with JEDEC programming and to protect the design from being copied or specifications reverse engineered. • Up to 2000 Gate Array Gates (6000 PLD equivalent gates)
P r o d u c t F a m i l y P r o f i l e
• Replaces up to 50 TTL Packages
A1010B A1020B
• Replaces up to twenty 20-Pin PAL® Packages
Device A10V10B A10V20B
• Design Library with over 250 Macro Functions Capacity Gate Array Equivalent Gates 1,200 2,000 • Gate Array Architecture Allows Completely Automatic PLD Equivalent Gates 3,000 6,000 Place and Route TTL Equivalent Packages 30 50 • Up to 547 Programmable Logic Modules 20-Pin PAL Equivalent Packages 12 20 • Up to 273 Flip-Flops Logic Modules 295 547 • Data Rates to 75 MHz Flip-Flops (maximum) 147 273 • Two In-Circuit Diagnostic Probe Pins Support Speed Routing Resources Analysis to 25 MHz Horizontal Tracks/Channel 22 22 Vertical Tracks/Column 13 13 • Built-In High Speed Clock Distribution Network PLICE Antifuse Elements 112,000 186,000 • I/O Drive to 10 mA (5 V), 6 mA (3.3 V) User I/Os (maximum) 57 69 • Nonvolatile, User Programmable Packages: 44 PLCC 44 PLCC 68 PLCC 68 PLCC • Fabricated in 1.0 micron CMOS technology 84 PLCC 100 PQFP 100 PQFP
D e s c r i p t i o n
80 VQFP 80 VQFP The ACT™ 1 Series of field programmable gate arrays 84 CPGA 84 CPGA (FPGAs) offers a variety of package, speed, and application 84 CQFP combinations. Devices are implemented in silicon gate, Performance 1-micron two-level metal CMOS, and they employ Actel’s 5 V Data Rate (maximum) 75 MHz 75 MHz PLICE® antifuse technology. The unique architecture offers 3.3 V Data Rate (maximum) 55 MHz 55 MHz gate array flexibility, high performance, and instant
Note:
See Product Plan on page 1-286 for package availability. turnaround through user programming. Device utilization is typically 95 to 100 percent of available logic modules.
T h e D e s i g n e r a n d D e s i g n e r
ACT 1 devices also provide system designers with unique
A d v a n t a g e ™ S y s t e m s
on-chip diagnostic probe capabilities, allowing convenient The ACT 1 device family is supported by Actel’s Designer and testing and debugging. Additional features include an on-chip Designer Advantage Systems, allowing logic design clock driver with a hardwired distribution network. The implementation with minimum effort. The systems offer network provides efficient clock distribution with minimum Microsoft® Windows™ and X Windows™ graphical user skew. interfaces and integrate with the resident CAE system to The user-definable I/Os are capable of driving at both TTL provide a complete gate array design environment: schematic and CMOS drive levels. Available packages include plastic capture, simulation, fully automatic place and route, timing and ceramic J-leaded chip carriers, ceramic and plastic quad verification, and device programming. The systems also ™ flatpacks, and ceramic pin grid array. include the ACTmap VHDL optimization and synthesis tool and the ACTgen™ Macro Builder, a powerful macro function generator for counters, adders, and other structural blocks.
A p r i l 1 9 9 6 1-283
© 1996 Actel Corporation Document Outline ACT™ 1 Series FPGAs Features Description Product Family Profile The Designer and Designer Advantage™ Systems ACT 1 Device Structure The ACT 1 Logic Module I/O Buffers Device Organization Probe Pin ACT 1 Array Performance Temperature and Voltage Effects Logic Module Size Ordering Information Product Plan Device Resources Pin Description Absolute Maximum Ratings1 Free air temperature range Recommended Operating Conditions Electrical Specifications (5V) Electrical Specifications (3.3V) Package Thermal Characteristics General Power Equation Static Power Component Active Power Component Equivalent Capacitance CEQ Values for Actel FPGAs Fixed Capacitance Values for Actel FPGAs (pF) Determining Average Switching Frequency Functional Timing Tests Output Buffer Performance Derating (5V) Output Buffer Performance Derating (3.3V) ACT 1 Timing Module* Predictable Performance: Tight Delay Distributions... Timing Characteristics Critical Nets and Typical Nets Long Tracks Timing Derating Timing Derating Factor (Temperature and Voltage) Timing Derating Factor for Designs at Typical Temp... Temperature and Voltage Derating Factors (normaliz... Temperature and Voltage Derating Factors (normaliz... Junction Temperature and Voltage Derating Curves (... Parameter Measurement Output Buffer Delays AC Test Loads Input Buffer Delays Module Delays Sequential Timing Characteristics Flip-Flops and Latches ACT 1 Timing Characteristics (Worst-Case Commercial Conditions, VCC = 4.75 V,T... ACT 1 Timing Characteristics (continued) (Worst-Case Commercial Conditions) ACT 1 Timing Characteristics (continued) (Worst-Case Commercial Conditions) Package Pin Assignments 44-Pin PLCC 68-Pin PLCC Package Pin Assignments (continued) 84-Pin PLCC Package Pin Assignments (continued) 100-Pin PQFP Package Pin Assignments (continued) 80-Pin VQFP Package Pin Assignments (continued) 84-Pin CPGA Package Pin Assignments (continued) 84-Pin CQFP