Datasheet AD7621 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 16-Bit, 2 LSB INL, 3 MSPS PulSAR® ADC |
| Pages / Page | 32 / 5 — AD7621. TIMING SPECIFICATIONS. Table 3. Parameter Symbol. Min. Typ. Max. … |
| File Format / Size | PDF / 627 Kb |
| Document Language | English |
AD7621. TIMING SPECIFICATIONS. Table 3. Parameter Symbol. Min. Typ. Max. Unit
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AD7621 TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3. Parameter Symbol Min Typ Max Unit
CONVERSION AND RESET (Refer to Figure 31 and Figure 32) Convert Pulse Width t1 15 701 ns Time Between Conversions (Warp2 Mode/Normal Mode/Impulse Mode)3 t2 333/500/800 ns CNVST Low to BUSY High Delay t3 23 ns BUSY High All Modes (Except Master Serial Read After Convert) t4 283/430/560 ns Aperture Delay t5 1 ns End of Conversion to BUSY Low Delay t6 10 ns Conversion Time (Warp Mode/Normal Mode/Impulse Mode) t7 283/430/560 ns Acquisition Time (Warp Mode/Normal Mode/Impulse Mode) t8 50/70/50 ns RESET Pulse Width t9 15 ns RESET Low to BUSY High Delay4 t38 10 ns BUSY High Time from RESET Low4 t39 600 ns PARALLEL INTERFACE MODES (Refer to Figure 33 and Figure 35) CNVST Low to DATA Valid Delay t10 283/430/560 ns (Warp Mode/Normal Mode/Impulse Mode) DATA Valid to BUSY Low Delay t11 2 ns Bus Access Request to DATA Valid t12 20 ns Bus Relinquish Time t13 2 15 ns MASTER SERIAL INTERFACE MODES5 (Refer to Figure 37 and Figure 38) CS Low to SYNC Valid Delay t14 10 ns CS Low to Internal SCLK Valid Delay5 t15 10 ns CS Low to SDOUT Delay t16 10 ns CNVST Low to SYNC Delay (Warp Mode/Normal Mode/Impulse Mode) t17 12/137/263 ns SYNC Asserted to SCLK First Edge Delay t18 0.5 ns Internal SCLK Period6 t19 8 12 ns Internal SCLK High6 t20 2 ns Internal SCLK Low6 t21 3 ns SDOUT Valid Setup Time6 t22 1 ns SDOUT Valid Hold Time6 t23 0 ns SCLK Last Edge to SYNC Delay6 t24 0 ns CS High to SYNC HI-Z t25 10 ns CS High to Internal SCLK HI-Z t26 10 ns CS High to SDOUT HI-Z t27 10 ns BUSY High in Master Serial Read after Convert6 t28 See Table 4 CNVST Low to SYNC Asserted Delay (All Modes) t29 275/400/500 ns SYNC Deasserted to BUSY Low Delay t30 13 ns Rev. 0 | Page 5 of 32 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS SERIAL CLOCK TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION MODES OF OPERATION TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS DRIVER AMPLIFIER CHOICE Single-to-Differential Driver VOLTAGE REFERENCE INPUT Internal Reference External 1.2 V Reference and Internal Buffer External Reference Reference Decoupling Temperature Sensor POWER SUPPLY Power Sequencing Power-Up POWER DISSIPATION VS. THROUGHPUT CONVERSION CONTROL INTERFACES DIGITAL INTERFACE RESET PARALLEL INTERFACE Master Parallel Interface Slave Parallel Interface 8-Bit Interface (Master or Slave) SERIAL INTERFACE MASTER SERIAL INTERFACE Internal Clock SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read After Conversion External Clock Data Read During Previous Conversion MICROPROCESSOR INTERFACING SPI Interface (ADSP-219x) APPLICATION LAYOUT EVALUATING THE AD7621 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
AD7621 TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3. Parameter Symbol Min Typ Max Unit
CONVERSION AND RESET (Refer to Figure 31 and Figure 32) Convert Pulse Width t1 15 701 ns Time Between Conversions (Warp2 Mode/Normal Mode/Impulse Mode)3 t2 333/500/800 ns CNVST Low to BUSY High Delay t3 23 ns BUSY High All Modes (Except Master Serial Read After Convert) t4 283/430/560 ns Aperture Delay t5 1 ns End of Conversion to BUSY Low Delay t6 10 ns Conversion Time (Warp Mode/Normal Mode/Impulse Mode) t7 283/430/560 ns Acquisition Time (Warp Mode/Normal Mode/Impulse Mode) t8 50/70/50 ns RESET Pulse Width t9 15 ns RESET Low to BUSY High Delay4 t38 10 ns BUSY High Time from RESET Low4 t39 600 ns PARALLEL INTERFACE MODES (Refer to Figure 33 and Figure 35) CNVST Low to DATA Valid Delay t10 283/430/560 ns (Warp Mode/Normal Mode/Impulse Mode) DATA Valid to BUSY Low Delay t11 2 ns Bus Access Request to DATA Valid t12 20 ns Bus Relinquish Time t13 2 15 ns MASTER SERIAL INTERFACE MODES5 (Refer to Figure 37 and Figure 38) CS Low to SYNC Valid Delay t14 10 ns CS Low to Internal SCLK Valid Delay5 t15 10 ns CS Low to SDOUT Delay t16 10 ns CNVST Low to SYNC Delay (Warp Mode/Normal Mode/Impulse Mode) t17 12/137/263 ns SYNC Asserted to SCLK First Edge Delay t18 0.5 ns Internal SCLK Period6 t19 8 12 ns Internal SCLK High6 t20 2 ns Internal SCLK Low6 t21 3 ns SDOUT Valid Setup Time6 t22 1 ns SDOUT Valid Hold Time6 t23 0 ns SCLK Last Edge to SYNC Delay6 t24 0 ns CS High to SYNC HI-Z t25 10 ns CS High to Internal SCLK HI-Z t26 10 ns CS High to SDOUT HI-Z t27 10 ns BUSY High in Master Serial Read after Convert6 t28 See Table 4 CNVST Low to SYNC Asserted Delay (All Modes) t29 275/400/500 ns SYNC Deasserted to BUSY Low Delay t30 13 ns Rev. 0 | Page 5 of 32 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS SERIAL CLOCK TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION MODES OF OPERATION TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS DRIVER AMPLIFIER CHOICE Single-to-Differential Driver VOLTAGE REFERENCE INPUT Internal Reference External 1.2 V Reference and Internal Buffer External Reference Reference Decoupling Temperature Sensor POWER SUPPLY Power Sequencing Power-Up POWER DISSIPATION VS. THROUGHPUT CONVERSION CONTROL INTERFACES DIGITAL INTERFACE RESET PARALLEL INTERFACE Master Parallel Interface Slave Parallel Interface 8-Bit Interface (Master or Slave) SERIAL INTERFACE MASTER SERIAL INTERFACE Internal Clock SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read After Conversion External Clock Data Read During Previous Conversion MICROPROCESSOR INTERFACING SPI Interface (ADSP-219x) APPLICATION LAYOUT EVALUATING THE AD7621 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
