Datasheet ADP1071-1, ADP1071-2 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | Isolated Synchronous Flyback Controller with Integrated iCoupler |
| Pages / Page | 12 / 4 — ADP1071-1/ADP1071-2. Preliminary Technical Data. SPECIFICATIONS. Table 1. … |
| Revision | PrA |
| File Format / Size | PDF / 417 Kb |
| Document Language | English |
ADP1071-1/ADP1071-2. Preliminary Technical Data. SPECIFICATIONS. Table 1. Parameter. Symbol. Test Conditions/Comments. Min. Typ. Max
Text Version of Document
ADP1071-1/ADP1071-2 Preliminary Technical Data SPECIFICATIONS
VIN =24V, VDD2 = 12 V, TA = −40°C to +125°C, unless otherwise noted.
Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit
SUPPLY (primary) Supply Voltage V 4.7 µF capacitor from Vin to PGND 4.7 24 60 V IN 1 µF capacitor from VREG1 to PGND Quiescent Supply Current I V > V , GATE pin unloaded VIN IN IN_UVLO At 100kHz 3.8 mA At 300kHz 4.4 mA At 600kHz 6.8 mA I V > V , GATE pin loaded with 2.2nF VIN IN IN_UVLO and 410pF respectively At 100kHz 5.5 mA At 300kHz 11 mA At 600kHz 22 mA VIN shutdown current V < 1.2 V, VREG1= 0V, VIN= 60 V 35 μA EN (VIN + VREG1) startup I V < 1.2 V, VREG1= 12 V, VIN= 12 V 160 µA VIN_startup EN current VIN rising 4.3 4.5 4.7 V VIN UVLO VIN falling 4.3 V -0.1 V UVLO hysteresis EN>1.2 V, 1 µF capacitor on VREG1 1 ms Time from EN high to GATE output switching EN<1.0 V, 1 µF capacitor on VREG1 1 µs Time from EN low to GATE output stops switching SUPPLY (secondary) Supply Voltage V 4.7 µF capacitor from VDD2 to PGND2 4.5 12 36 V DD2 1 µF capacitor from VREG2 to PGND2 Quiescent supply current I SR1 unloaded DD2 At 100kHz 6.3 mA At 300kHz 6.4 mA At 600kHz 6.9 mA I SR loaded with 2.2nF DD2 At 100kHz 8 mA At 300kHz 13.5 mA At 600kHz 18 mA UVLO threshold V rising 3.5 V DD2 V falling 3.45 V DD2 UVLO Hysteresis 50 mV Secondary UVLO hiccup time 225 ms OSCILLATOR Switching frequency (f ) R = 480 kΩ (±1%) -10% 50 +10% kHz s RT R = 240 kΩ (±1%) -10% 100 +10% kHz RT R = 120 kΩ (±1%) -10% 200 +10% kHz RT R = 80 kΩ (±1%) -10% 300 +10% kHz RT R = 60 kΩ (±1%) -10% 400 +10% kHz RT R = 40 kΩ (±1%) -10% 600 +10% kHz RT VREG1 pin VREG1 voltage clamp I = 3mA, V < 1.2 V 13.5 14.3 15.2 V VREG1 EN VREG1 clamp series VREG1 current 5mA and 10mA 16 Ω resistance Rev. PrA | Page 4 of 12 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS TYPICAL APPLICATION CIRCUITS SPECIFICATIONS REGULATORY INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS SIMPLIFIED BLOCK DIAGRAM APPLICATIONS INFORMATION INSULATION LIFETIME OUTLINE DIMENSIONS
VIN =24V, VDD2 = 12 V, TA = −40°C to +125°C, unless otherwise noted.
Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit
SUPPLY (primary) Supply Voltage V 4.7 µF capacitor from Vin to PGND 4.7 24 60 V IN 1 µF capacitor from VREG1 to PGND Quiescent Supply Current I V > V , GATE pin unloaded VIN IN IN_UVLO At 100kHz 3.8 mA At 300kHz 4.4 mA At 600kHz 6.8 mA I V > V , GATE pin loaded with 2.2nF VIN IN IN_UVLO and 410pF respectively At 100kHz 5.5 mA At 300kHz 11 mA At 600kHz 22 mA VIN shutdown current V < 1.2 V, VREG1= 0V, VIN= 60 V 35 μA EN (VIN + VREG1) startup I V < 1.2 V, VREG1= 12 V, VIN= 12 V 160 µA VIN_startup EN current VIN rising 4.3 4.5 4.7 V VIN UVLO VIN falling 4.3 V -0.1 V UVLO hysteresis EN>1.2 V, 1 µF capacitor on VREG1 1 ms Time from EN high to GATE output switching EN<1.0 V, 1 µF capacitor on VREG1 1 µs Time from EN low to GATE output stops switching SUPPLY (secondary) Supply Voltage V 4.7 µF capacitor from VDD2 to PGND2 4.5 12 36 V DD2 1 µF capacitor from VREG2 to PGND2 Quiescent supply current I SR1 unloaded DD2 At 100kHz 6.3 mA At 300kHz 6.4 mA At 600kHz 6.9 mA I SR loaded with 2.2nF DD2 At 100kHz 8 mA At 300kHz 13.5 mA At 600kHz 18 mA UVLO threshold V rising 3.5 V DD2 V falling 3.45 V DD2 UVLO Hysteresis 50 mV Secondary UVLO hiccup time 225 ms OSCILLATOR Switching frequency (f ) R = 480 kΩ (±1%) -10% 50 +10% kHz s RT R = 240 kΩ (±1%) -10% 100 +10% kHz RT R = 120 kΩ (±1%) -10% 200 +10% kHz RT R = 80 kΩ (±1%) -10% 300 +10% kHz RT R = 60 kΩ (±1%) -10% 400 +10% kHz RT R = 40 kΩ (±1%) -10% 600 +10% kHz RT VREG1 pin VREG1 voltage clamp I = 3mA, V < 1.2 V 13.5 14.3 15.2 V VREG1 EN VREG1 clamp series VREG1 current 5mA and 10mA 16 Ω resistance Rev. PrA | Page 4 of 12 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS TYPICAL APPLICATION CIRCUITS SPECIFICATIONS REGULATORY INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS SIMPLIFIED BLOCK DIAGRAM APPLICATIONS INFORMATION INSULATION LIFETIME OUTLINE DIMENSIONS
