Datasheet ADP1071-1, ADP1071-2 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | Isolated Synchronous Flyback Controller with Integrated iCoupler |
| Pages / Page | 12 / 5 — Preliminary Technical Data. ADP1071-1/ADP1071-2. Parameter. Symbol. Test … |
| Revision | PrA |
| File Format / Size | PDF / 417 Kb |
| Document Language | English |
Preliminary Technical Data. ADP1071-1/ADP1071-2. Parameter. Symbol. Test Conditions/Comments. Min. Typ. Max. Unit
Text Version of Document
Preliminary Technical Data ADP1071-1/ADP1071-2 Parameter Symbol Test Conditions/Comments Min Typ Max Unit
GATE drivers (primary) GATE high voltage I = 20mA, VIN > 9V (ADP1071-2 only) 7.6 8 8.4 V VREG1 Gate short circuit peak 8 V on VREG1 1.0 A current1 GATE Rise Time C = 2.2 nF, 10% to 90% 16 ns GATE GATE Fall Time C = 2.2 nF, 90% to 10% 16 ns GATE GATE R R Source 100mA 6 Ω ON ON_SOURCE GATE R R Sink 100mA 4 Ω ON ON_SINK GATE Max Duty Cycle 85 % GATE minimum on time At 300 kHz, includes blanking time 150 ns SR driver (secondary) SR high voltage I = 15mA, VDD2 > 5.5V 4.7 5 5.3 V VREG2 SR short circuit peak current2 5 V on VREG2 1.0 A SR Rise Time C = 2.2 nF, 10% to 90% 16 ns SR SR Fall Time C = 2.2 nF, 90% to 10% 16 ns SR SR minimum on time At 300 kHz 120 ns SR R R Source 100mA 6 Ω ON ON_SR_SOURCE R Sink 100mA 4 1 Ω ON_SR_SINK Deadtime Setting GATE to SR Deadtime between SR falling and GATE 25 ns rising Deadtime between GATE falling and SR 50 ns rising CURRENT LIMIT SENSE (primary) CS limit threshold V Over current sense limit threshold 120 mV CS_LIM CS leading edge blanking 150 ns time 20 µA/Ts Current source di/dt for slope compensation 12 Current sense amplifier gain 0.5 2.5 Current sense amplifier limit 20 ns OCP comparator delay 1.25 ms Time in OCP before entering hiccup mode 45 ms OCP hiccup time FB PIN AND ERROR AMPLIFIER Feedback Accuracy Voltage V FB T = −40°C to +85°C −0.85% +1.2 +0.85% V J T = −40°C to +125°C −1.5% +1.2 +1.5% V J FB Input Bias Current -100 1 +100 nA Transconductance gm 212 250 287 μs Output current clamp -65 μA minimum Output current clamp 40 μA maximum COMP clamp maximum 2.52 V voltage COMP clamp minimum 0.6 V voltage Open loop gain 80 dB Output shunt resistance 50 GΩ Gain Bandwidth Product 1 MHz PRECISION ENABLE THRESHOLD EN threshold V EN rising 1.14 1.2 1.26 V EN EN hysteresis V < 1.2 V 3 4 5 mA EN V > 1.2 V 1 µA EN EN Hysteresis current 3 µA Rev. PrA | Page 5 of 12 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS TYPICAL APPLICATION CIRCUITS SPECIFICATIONS REGULATORY INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS SIMPLIFIED BLOCK DIAGRAM APPLICATIONS INFORMATION INSULATION LIFETIME OUTLINE DIMENSIONS
GATE drivers (primary) GATE high voltage I = 20mA, VIN > 9V (ADP1071-2 only) 7.6 8 8.4 V VREG1 Gate short circuit peak 8 V on VREG1 1.0 A current1 GATE Rise Time C = 2.2 nF, 10% to 90% 16 ns GATE GATE Fall Time C = 2.2 nF, 90% to 10% 16 ns GATE GATE R R Source 100mA 6 Ω ON ON_SOURCE GATE R R Sink 100mA 4 Ω ON ON_SINK GATE Max Duty Cycle 85 % GATE minimum on time At 300 kHz, includes blanking time 150 ns SR driver (secondary) SR high voltage I = 15mA, VDD2 > 5.5V 4.7 5 5.3 V VREG2 SR short circuit peak current2 5 V on VREG2 1.0 A SR Rise Time C = 2.2 nF, 10% to 90% 16 ns SR SR Fall Time C = 2.2 nF, 90% to 10% 16 ns SR SR minimum on time At 300 kHz 120 ns SR R R Source 100mA 6 Ω ON ON_SR_SOURCE R Sink 100mA 4 1 Ω ON_SR_SINK Deadtime Setting GATE to SR Deadtime between SR falling and GATE 25 ns rising Deadtime between GATE falling and SR 50 ns rising CURRENT LIMIT SENSE (primary) CS limit threshold V Over current sense limit threshold 120 mV CS_LIM CS leading edge blanking 150 ns time 20 µA/Ts Current source di/dt for slope compensation 12 Current sense amplifier gain 0.5 2.5 Current sense amplifier limit 20 ns OCP comparator delay 1.25 ms Time in OCP before entering hiccup mode 45 ms OCP hiccup time FB PIN AND ERROR AMPLIFIER Feedback Accuracy Voltage V FB T = −40°C to +85°C −0.85% +1.2 +0.85% V J T = −40°C to +125°C −1.5% +1.2 +1.5% V J FB Input Bias Current -100 1 +100 nA Transconductance gm 212 250 287 μs Output current clamp -65 μA minimum Output current clamp 40 μA maximum COMP clamp maximum 2.52 V voltage COMP clamp minimum 0.6 V voltage Open loop gain 80 dB Output shunt resistance 50 GΩ Gain Bandwidth Product 1 MHz PRECISION ENABLE THRESHOLD EN threshold V EN rising 1.14 1.2 1.26 V EN EN hysteresis V < 1.2 V 3 4 5 mA EN V > 1.2 V 1 µA EN EN Hysteresis current 3 µA Rev. PrA | Page 5 of 12 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS TYPICAL APPLICATION CIRCUITS SPECIFICATIONS REGULATORY INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS SIMPLIFIED BLOCK DIAGRAM APPLICATIONS INFORMATION INSULATION LIFETIME OUTLINE DIMENSIONS
