Datasheet LTC1090 (Analog Devices) - 2

ManufacturerAnalog Devices
DescriptionSingle Chip 10-Bit Data Acquisition System
Pages / Page28 / 2 — ABSOLUTE AXI U RATI GS. PACKAGE/ORDER I FOR ATIO. (Notes 1 and 2). …
File Format / SizePDF / 356 Kb
Document LanguageEnglish

ABSOLUTE AXI U RATI GS. PACKAGE/ORDER I FOR ATIO. (Notes 1 and 2). (OBSOLETE). OBSOLETE PACKAGE. RECO E DED OPERATI G CO DITIO S

ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO (Notes 1 and 2) (OBSOLETE) OBSOLETE PACKAGE RECO E DED OPERATI G CO DITIO S

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LTC1090
W W W U U W U ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO (Notes 1 and 2)
TOP VIEW Supply Voltage (V ORDER PART CC) to GND or V – .. 12V CH0 1 20 VCC Negative Supply Voltage (V –) ... – 6V to GND NUMBER CH1 2 19 ACLK Voltage: CH2 3 18 SCLK Analog and Reference LTC1090ACN CH3 4 17 DIN Inputs .. (V –) –0.3V to V LTC1090CN CC 0.3V CH4 5 16 DOUT Digital Inputs ... –0.3V to 12V LTC1090CSW CH5 6 15 CS Digital Outputs .. – 0.3V to VCC 0.3V CH6 7 14 REF+ Power Dissipation .. 500mW CH7 8 13 REF– Operating Temperature Range COM 9 12 V – LTC1090AC/LTC1090C ..–40°C to 85°C DGND 10 11 AGND LTC1090AM/LTC1090M
(OBSOLETE)
.. –55°C to 125°C SW PACKAGE N PACKAGE Storage Temperature Range ... – 65°C to 150°C 20-LEAD PLASTIC SO WIDE 20-LEAD PDIP T Lead Temperature (Soldering, 10 sec).. 300°C JMAX = 150°C, θJA = 70°C/W TJMAX = 110°C, θJA = 90°C/W J PACKAGE LTC1090AMJ 20-LEAD CERDIP LTC1090MJ TJMAX = 150°C θJA = 70° C/W LTC1090ACJ LTC1090CJ
OBSOLETE PACKAGE
Consider the SW or N Package for Alternate Source LTC1090 • POI01 Consult LTC Marketing for parts specified with wider operating temperature ranges.
WW U U U U RECO E DED OPERATI G CO DITIO S LTC1090/LTC1090A SYMBOL PARAMETER CONDITIONS MIN MAX UNITS
VCC Positive Supply Voltage V– = 0V 4.5 10 V V– Negative Supply Voltage VCC = 5V – 5.5 0 V fSCLK Shift Clock Frequency VCC = 5V 0 1.0 MHz fACLK A/D Clock Frequency VCC = 5V 25°C 0.01 2.0 MHz 85°C 0.05 2.0 125°C 0.25 2.0 tCYC Total Cycle Time See Operating Sequence 10 SCLK + Cycles 48 ACLK thCS Hold Time, CS Low After Last SCLK↓ VCC = 5V 0 ns thDI Hold Time, DIN After SCLK↑ VCC = 5V 150 ns tsuCS Setup Time CS↓ Before Clocking in First Address Bit (Note 9) VCC = 5V 2 ACLK Cycles 1µs tsuDI Setup Time, DIN Stable Before SCLK↑ VCC = 5V 400 ns tWHACLK ACLK High Time VCC = 5V 127 ns tWLACLK ACLK Low Time VCC = 5V 200 ns tWHCS CS High Time During Conversion VCC = 5V 44 ACLK Cycles 1090fc 2
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