Datasheet AD9480 (Analog Devices) - 9

ManufacturerAnalog Devices
Description8-Bit, 250 MSPS, 3.3 V A/D Converter
Pages / Page29 / 9 — AD9480. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. AGND. LVDSBIAS. …
RevisionA
File Format / SizePDF / 650 Kb
Document LanguageEnglish

AD9480. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. AGND. LVDSBIAS. AVDD. VIN+. VIN–. VREF. 44 43 42. 40 39 38. CLK+. SENSE. CLK–. PIN 1. DRVDD

AD9480 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AGND LVDSBIAS AVDD VIN+ VIN– VREF 44 43 42 40 39 38 CLK+ SENSE CLK– PIN 1 DRVDD

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AD9480 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AGND NC LVDSBIAS AVDD AGND VIN+ VIN– AGND AVDD AGND VREF 44 43 42 41 40 39 38 37 36 35 34 CLK+ 1 33 SENSE CLK– 2 PIN 1 32 AGND AVDD 3 31 AVDD AGND 4 30 AGND AD9480 DRVDD 5 29 PDWN TOP VIEW DRGND 6 (Not to Scale) 28 S1 D0_C (LSB) 7 27 DRGND D0_T (LSB) 8 26 D7_T (MSB) D1_C 9 25 D7_C (MSB) D1_T 10 24 D6_T D2_C 11 23 D6_C 12 13 14 15 16 17 18 19 20 21 22 NC = NO CONNECT 2_T 3_C 3_T 4_C 4_T 5_C 5_T
003
D D D DCO DCO+ D D D D DRGND DRVDD
04619- Figure 3. Pin Configuration
Table 7. Pin Function Descriptions Pin Pin No. Mnemonic Description No. Mnemonic Description
1 CLK+ Input Clock—True 23 D6_C Data Output Bit 6—Complement 2 CLK− Input Clock—Complement 24 D6_T Data Output Bit 6—True 3 AVDD 3.3 V Analog Supply 25 D7_C Data Output Bit 7—Complement (MSB) 4 AGND Analog Ground 26 D7_T Data Output Bit 7—True (MSB) 5 DRVDD 3.3 V Digital Output Supply 27 DRGND Digital Ground 6 DRGND Digital Ground 28 S1 Data Format Select and Duty-Cycle Stabilizer Selection (See Table 8) 7 D0_C Data Output Bit 0—Complement (LSB) 29 PDWN Power-Down Selection (AVDD = Power Down) 8 D0_T Data Output Bit 0—True (LSB) 30 AGND Analog Ground 9 D1_C Data Output Bit 1—Complement 31 AVDD 3.3 V Analog Supply 10 D1_T Data Output Bit 1—True 32 AGND Analog Ground 11 D2_C Data Output Bit 2—Complement 33 SENSE Reference Mode Selection (See Table 9) 12 D2_T Data Output Bit 2—True 34 VREF Voltage Reference Input/Output 13 D3_C Data Output Bit 3—Complement 35 AGND Analog Ground 14 D3_T Data Output Bit 3—True 36 AVDD 3.3 V Analog Supply 15 DRGND Digital Ground 37 AGND Analog Ground 16 DCO− Data Clock Output—Complement 38 VIN− Analog Input—Complement 17 DCO+ Data Clock Output—True 39 VIN+ Analog Input—True 18 DRVDD 3.3 V Digital Output Supply 40 AGND Analog Ground 19 D4_C Data Output Bit 4—Complement 41 AVDD 3.3 V Analog Supply 20 D4_T Data Output Bit 4—True 42 LVDSBIAS LVDS Output Current Adjust 21 D5_C Data Output Bit 5—Complement 43 NC1 No Connect (Leave Floating) 22 D5_T Data Output Bit 5—True 44 AGND Analog Ground 1 Pin 43 will self-bias to 1.5 V. It can be left floating (as recommended) or tied to AVDD or ground with no ill effects. Rev. A | Page 8 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY DC SPECIFICATIONS DIGITAL SPECIFICATIONS AC SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS APPLICATION NOTES CLOCKING THE AD9480 ANALOG INPUTS VOLTAGE REFERENCE Fixed Reference External Reference Programmable Reference DIGITAL OUTPUTS OUTPUT CODING INTERLEAVING TWO AD9480s DATA CLOCK OUT POWER-DOWN AD9480 EVALUATION BOARD POWER CONNECTOR ANALOG INPUTS GAIN OPTIONAL OPERATIONAL AMPLIFIER CLOCK OPTIONAL CLOCK BUFFER OPTIONAL XTAL VOLTAGE REFERENCE DATA OUTPUTS EVALUATION BOARD BILL OF MATERIALS (BOM) PCB SCHEMATICS PCB LAYERS OUTLINE DIMENSIONS ORDERING GUIDE