Datasheet AD9480 (Analog Devices) - 10

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AD9480 TERMINOLOGY Analog Bandwidth Full-Scale Input Power
The analog input frequency at which the spectral power of the Expressed in dBm. Computed by fundamental frequency (as determined by the FFT analysis) is 2 reduced by 3 dB.

⎛ V FULLSCALE rms ⎞ ⎜ ⎟ ⎜ Z ⎟ INPUT
Aperture Delay
Power = 10 log FULLSCALE ⎜ ⎟ ⎜ 0.001 ⎟ The delay between the 50% point of the rising edge of the ⎜ ⎟ encode command and the instant the analog input is sampled.

⎝ ⎠
Aperture Uncertainty (Jitter) Gain Error
The sample-to-sample variation in aperture delay. The difference between the measured and ideal full-scale input voltage range of the ADC.
Clock Pulse Width/Duty Cycle
Pulse width high is the minimum amount of time that the
Harmonic Distortion, Second
clock pulse should be left in a Logic 1 state to achieve rated The ratio of the rms signal amplitude to the rms value of the performance; pulse width low is the minimum time that the second harmonic component, reported in dBc. clock pulse should be left in a low state. See the timing
Harmonic Distortion, Third
implications of changing tEH in the Clocking the AD9480 The ratio of the rms signal amplitude to the rms value of the section. At a given clock rate, these specifications define an third harmonic component, reported in dBc. acceptable clock duty cycle.
Integral Nonlinearity Crosstalk
The deviation of the transfer function from a reference line Coupling onto one channel being driven by a low level measured in fractions of 1 LSB using a best straight line (−40 dBFS) signal when the adjacent interfering channel determined by a least square curve fit. is driven by a full-scale signal.
Minimum Conversion Rate Differential Analog Input Resistance, Differential Analog
The encode rate at which the SNR of the lowest analog
Input Capacitance, and Differential Analog Input Impedance
signal frequency drops by no more than 3 dB below the The real and complex impedances measured at each analog guaranteed limit. input port. The resistance is measured statically, and the capacitance and differential input impedances are measured
Maximum Conversion Rate
with a network analyzer. The encode rate at which parametric testing is performed.
Differential Analog Input Voltage Range Output Propagation Delay
The peak-to-peak differential voltage that must be applied to The delay between a differential crossing of CLK+ and the converter to generate a full-scale response. Peak differential CLK− and the time when all output data bits are within voltage is computed by observing the voltage on a single pin valid logic levels. and subtracting the voltage from the other pin, which is 180° out of phase. Peak-to-peak differential is computed by rotating
Noise (For Any Range Within the ADC)
the inputs phase 180° and taking the peak measurement again. This value includes both thermal and quantization noise. The difference is then computed between both peak FS − measurements. ⎛ SNR − Signal ⎞ V = Z × .001×10

noise ⎜⎜ dBm dBc dBFS ⎟⎟ ⎝ 10 ⎠
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step. where: Z is the input impedance.
Effective Number of Bits
FS is the full scale of the device for the frequency in question. The effective number of bits (ENOB) is calculated by the SNR is the value for the particular input level. measured SINAD based on (assuming full-scale input) Signal is the signal level within the ADC reported in dB below SINAD − 1.76 dB full scale. ENOB = MEASURED 6.02
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in power supply voltage. Rev. A | Page 9 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY DC SPECIFICATIONS DIGITAL SPECIFICATIONS AC SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS APPLICATION NOTES CLOCKING THE AD9480 ANALOG INPUTS VOLTAGE REFERENCE Fixed Reference External Reference Programmable Reference DIGITAL OUTPUTS OUTPUT CODING INTERLEAVING TWO AD9480s DATA CLOCK OUT POWER-DOWN AD9480 EVALUATION BOARD POWER CONNECTOR ANALOG INPUTS GAIN OPTIONAL OPERATIONAL AMPLIFIER CLOCK OPTIONAL CLOCK BUFFER OPTIONAL XTAL VOLTAGE REFERENCE DATA OUTPUTS EVALUATION BOARD BILL OF MATERIALS (BOM) PCB SCHEMATICS PCB LAYERS OUTLINE DIMENSIONS ORDERING GUIDE