Datasheet AD7703 (Analog Devices) - 8

AD7703 GENERAL DESCRIPTION
4. A 1-bit A/D converter (comparator) The AD7703 is a 20-bit A/D converter with on-chip digital 5. A 1-bit DAC filtering, intended for the measurement of wide dynamic range, low frequency signals such as those representing chemical, 6. A digital low-pass filter physical, or biological processes. It contains a charge-balancing
S/H AMP
(⌺-⌬) ADC, calibration microcontroller with on-chip static
COMPARATOR
RAM, clock oscillator, and serial communications port.
ANALOG LOW-PASS FILTER DIGITAL
The analog input signal to the AD7703 is continuously sampled
FILTER
at a rate determined by the frequency of the master clock, CLKIN. A charge-balancing A/D converter (⌺-⌬ modulator) converts
DIGITAL DATA DAC
the sampled signal into a digital pulse train whose duty cycle contains the digital information. A six-pole Gaussian digital low-pass filter processes the output of the ⌺-⌬ modulator and Figure 8. General ⌺-⌬ ADC updates the 20-bit output register at a 4 kHz rate. The output data can be read from the serial port randomly or periodically at In operation, the analog signal sample is fed to the subtracter, any rate up to 4 kHz. along with the output of the 1-bit DAC. The filtered difference signal is fed to the comparator, whose output samples the differ- ence signal at a frequency many times that of the analog signal
+5V ANALOG AV DV
sampling frequency (oversampling).
DD DD SUPPLY 0.1
␮
F 10
␮
F 0.1
␮
F SLEEP
Oversampling is fundamental to the operation of ⌺-⌬ ADCs. Using the quantization noise formula for an ADC
MODE 2.5V DRDY DATA READY
SNR = (6.02 ¥ number of bits + 1.76) dB
VOLTAGE VREF REFERENCE READ CS AD7703 (TRANSMIT)
a 1-bit ADC or comparator yields an SNR of 7.78 dB.
SCLK SERIAL CLOCK
The AD7703 samples the input signal at 16 kHz, which spreads
RANGE BP/UP SELECT SDATA SERIAL DATA
the quantization noise from 0 kHz to 8 kHz. Since the specified
CAL CALIBRATE
analog input bandwidth of the AD7703 is only 0 Hz to 10 Hz, the
CLKIN
noise energy in this bandwidth would be only 1/800 of the total
ANALOG AIN CLKOUT
quantization noise, even if the noise energy were spread evenly
INPUT SC1
throughout the spectrum. It is reduced still further by analog
ANALOG AGND SC2
filtering in the modulator loop, which shapes the quantization
GROUND 0.1 DGND
␮
F 0.1
␮
F
noise spectrum to move most of the noise energy to frequencies
AVSS DVSS
above 10 Hz. The SNR performance in the 0 Hz to 10 Hz range
–5V ANALOG
is conditioned to the 20-bit level in this fashion.
SUPPLY 10
␮
F
The output of the comparator provides the digital input for the 1-bit DAC, so the system functions as a negative feedback loop Figure 7. Typical System Connection Diagram that minimizes the difference signal. The digital data that repre- The AD7703 can perform self-calibration using the on-chip sents the analog input voltage is in the duty cycle of the pulse train calibration microcontroller and SRAM to store calibration appearing at the output of the comparator. It can be retrieved as parameters. A calibration cycle may be initiated at any time a parallel binary data-word using a digital filter. using the CAL control input. ⌺-⌬ ADCs are generally described by the order of the analog Other system components may also be included in the calibra- low-pass filter. A simple example of a first-order, ⌺-⌬ ADC is tion loop to remove offset and gain errors in the input channel. shown in Figure 8. This contains only a first-order, low-pass For battery operation, the AD7703 also offers a standby mode filter or integrator. It also illustrates the derivation of the alter- that reduces idle power consumption to typically 10 µW. native name for these devices: charge-balancing ADCs. The AD7703 uses a second-order, ⌺-⌬ modulator and a sophis-
THEORY OF OPERATION
ticated digital filter that provides a rolling average of the sampled The general block diagram of a ⌺-⌬ ADC is shown in Figure 8. output. After power-up or if there is a step change in the input It contains the following elements: voltage, there is a settling time that must elapse before valid 1. A sample-hold amplifier data is obtained. 2. A differential amplifier or subtracter 3. An analog low-pass filter REV. E –7– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE TIMING CHARACTERISTICS DEFINITION OF TERMS Linearity Error Differential Linearity Error Positive Full-Scale Error Unipolar Offset Error Bipolar Zero Error Bipolar Negative Full-Scale Error Positive Full-Scale Overrange Negative Full-Scale Overrange Offset Calibration Range Full-Scale Calibration Range Input Span PIN CONFIGURATION DIP, CERDIP, SOIC PIN FUNCTION DESCRIPTIONS GENERAL DESCRIPTION THEORY OF OPERATION DIGITAL FILTERING FILTER CHARACTERISTICS USING THE AD7703 SYSTEM DESIGN CONSIDERATIONS CLOCKING ANALOG INPUT RANGES ACCURACY AUTOCALIBRATION Initiating Calibration Span and Offset Limits POWER-UP AND CALIBRATION Drift Considerations INPUT SIGNAL CONDITIONING Source Resistance Antialias Considerations VOLTAGE REFERENCE CONNECTIONS POWER SUPPLIES AND GROUNDING SLEEP MODE DIGITAL INTERFACE Synchronous Self-Clocking Mode (SSC) Synchronous External Clock Mode (SEC) DIGITAL NOISE AND OUTPUT LOADING OUTLINE DIMENSIONS REVISION HISTORY