Datasheet LTC3765 (Analog Devices) - 6

LTC3765
PIN FUNCTIONS PGND (Pin 1):
Power Ground. Ground return for the high
RUN (Pin 12):
Run Control and Undervoltage Lockout current gate drivers. (UVLO). Connect to a resistor divider to monitor the input
PG (Pin 2):
Primary Gate. Gate drive for the primary voltage VIN, which is required for proper operation of switch NMOS. the Direct Flux Limit. Converter operation is enabled for VRUN > 1.25V. Hysteresis is a fixed 50mV with an additional
VCC (Pin 3):
Main Supply Pin. A ceramic bypass capacitor 5µA hysteresis current that combines with the resistor should be tied between this pin and ground. divider to comprise the total UVLO hysteresis voltage.
AG (Pin 4):
Active Gate. Gate drive for the active clamp
SSFLT (Pin 13):
Combination Soft-Start and Fault Indica- PMOS. This drive output is “in phase” with the PG out- tor. A capacitor to ground sets the duty cycle ramp-up put. Connect to the gate of a PMOS through a capacitive rate during primary-side start-up. To indicate a fault, the level-shift circuit. SSFLT pin is momentarily pulled above 6V.
ISMAG (Pin 5):
Magnetizing Current Sense Pin. Connect
NDRV (Pin 14):
Drive for External Linear Regulator. Con- to a current sense resistor in series with the source of nect to the gate of an NMOS and connect a pull-up resistor the active clamp PMOS. This pin limits the magnetizing to the main input voltage, VIN. An internal charge pump current of the main transformer to prevent core saturation drives this pin above VIN for low input voltage applications. when the active clamp is on.
IN+, IN– (Pin 15, Pin 16):
Inputs from Pulse Transformer.
DELAY (Pin 6):
Primary Gate Rising Delay Adjustment. A Connect through a DC restoring capacitor to the output resistor from this pin to ground sets the AG rising to PG winding of a pulse transformer. The input winding of the rising dead time, which is critical for optimizing efficiency. pulse transformer is driven by the LTC3766. After perform-
I – +
ing an initial open-loop start-up, the LTC3765 detects and
S , IS (Pin 7, Pin 8):
Inputs to the Overcurrent Compara- tor. Connect across a current sense resistor in series with decodes pulse encoded PWM information at these pins, the source of the primary NMOS. and then turns control of the PG and AG switching over to the LTC3766 secondary-side controller. Additionally,
FS/UV (Pin 10):
Oscillator Frequency Set and Undervolt- an internal bridge rectifier on the IN+/IN– pins extracts age Indicator. A resistor to ground sets the switching DC power from the pulse transformer and delivers it to frequency during start-up. When the RUN pin is low, the V the V CC pin. CC supply is undervoltage, or the overtemperature protection is active, a 50µA current source pulls this pin
SGND (Pin 9, Exposed Pad Pin 17):
Signal Ground. The to the lesser of V exposed pad metal of the package provides good thermal CC and 5V as an indicator. contact to the printed circuit board. It must be soldered to
RCORE (Pin 11):
Transformer Core Saturation Limit. A a ground plane for rated thermal performance. resistor from RCORE to ground proportional to transformer core parameters internally replicates the magnetizing cur- rent slope when the primary NMOS is on. This slope in combination with the voltage on the ISMAG and RUN pins limits the on-time of the NMOS to prevent saturation. See Applications Information. 3765fb 6 For more information www.linear.com/LTC3765 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts