Datasheet ATtiny11, ATtiny12 - Summary (Atmel) - 4
| Manufacturer | Atmel |
| Description | 8-bit AVR Microcontroller with 1K Byte Flash |
| Pages / Page | 15 / 4 — ATtiny12 Block Diagram. Figure 2. ATtiny11/12 |
| File Format / Size | PDF / 235 Kb |
| Document Language | English |
ATtiny12 Block Diagram. Figure 2. ATtiny11/12
Model Line for this Datasheet
Text Version of Document
ATtiny12 Block Diagram
Figure 2 on page 4. The ATtiny12 provides the following features: 1K bytes of Flash, 64 bytes EEPROM, up to six general-purpose I/O lines, 32 general-purpose working regis- ters, an 8-bit timer/counter, internal and external interrupts, programmable Watchdog Timer with internal oscillator, and two software-selectable power-saving modes. The Idle Mode stops the CPU while allowing the timer/counters and interrupt system to con- tinue functioning. The Power-down Mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. The wake-up or interrupt on pin change features enable the ATtiny12 to be highly responsive to external events, still featuring the lowest power consumption while in the power-down modes. The device is manufactured using Atmel’s high-density nonvolatile memory technology. By combining an RISC 8-bit CPU with Flash on a monolithic chip, the Atmel ATtiny12 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications.
Figure 2.
The ATtiny12 Block Diagram VCC 8-BIT DATA BUS INTERNAL INTERNAL OSCILLATOR CALIBRATED OSCILLATOR GND PROGRAM STACK WATCHDOG TIMING AND COUNTER POINTER TIMER CONTROL PROGRAM HARDWARE MCU CONTROL FLASH STACK REGISTER INSTRUCTION MCU STATUS REGISTER REGISTER GENERAL- PURPOSE REGISTERS INSTRUCTION TIMER/ DECODER Z COUNTER CONTROL INTERRUPT ALU LINES UNIT STATUS EEPROM REGISTER PROGRAMMING OSCILLATORS SPI LOGIC R O T DATA REGISTER DATA DIR. + - PORTB REG. PORTB ARA ANALOG COMP PORTB DRIVERS PB0-PB5
4 ATtiny11/12
1006FS–AVR–06/07 Document Outline Features Pin Configuration Overview ATtiny11 Block Diagram ATtiny12 Block Diagram Pin Descriptions VCC GND Port B (PB5..PB0) XTAL1 XTAL2 RESET Register Summary ATtiny11 Register Summary ATtiny12 Instruction Set Summary Ordering Information ATtiny11 ATtiny12 Packaging Information 8P3 8S2 Datasheet Revision History Rev. 1006F-06/07 Rev. 1006E-07/06 Rev. 1006D-07/03 Rev. 1006C-09/01
Figure 2 on page 4. The ATtiny12 provides the following features: 1K bytes of Flash, 64 bytes EEPROM, up to six general-purpose I/O lines, 32 general-purpose working regis- ters, an 8-bit timer/counter, internal and external interrupts, programmable Watchdog Timer with internal oscillator, and two software-selectable power-saving modes. The Idle Mode stops the CPU while allowing the timer/counters and interrupt system to con- tinue functioning. The Power-down Mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. The wake-up or interrupt on pin change features enable the ATtiny12 to be highly responsive to external events, still featuring the lowest power consumption while in the power-down modes. The device is manufactured using Atmel’s high-density nonvolatile memory technology. By combining an RISC 8-bit CPU with Flash on a monolithic chip, the Atmel ATtiny12 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications.
Figure 2.
The ATtiny12 Block Diagram VCC 8-BIT DATA BUS INTERNAL INTERNAL OSCILLATOR CALIBRATED OSCILLATOR GND PROGRAM STACK WATCHDOG TIMING AND COUNTER POINTER TIMER CONTROL PROGRAM HARDWARE MCU CONTROL FLASH STACK REGISTER INSTRUCTION MCU STATUS REGISTER REGISTER GENERAL- PURPOSE REGISTERS INSTRUCTION TIMER/ DECODER Z COUNTER CONTROL INTERRUPT ALU LINES UNIT STATUS EEPROM REGISTER PROGRAMMING OSCILLATORS SPI LOGIC R O T DATA REGISTER DATA DIR. + - PORTB REG. PORTB ARA ANALOG COMP PORTB DRIVERS PB0-PB5
4 ATtiny11/12
1006FS–AVR–06/07 Document Outline Features Pin Configuration Overview ATtiny11 Block Diagram ATtiny12 Block Diagram Pin Descriptions VCC GND Port B (PB5..PB0) XTAL1 XTAL2 RESET Register Summary ATtiny11 Register Summary ATtiny12 Instruction Set Summary Ordering Information ATtiny11 ATtiny12 Packaging Information 8P3 8S2 Datasheet Revision History Rev. 1006F-06/07 Rev. 1006E-07/06 Rev. 1006D-07/03 Rev. 1006C-09/01
