Datasheet ACT 1 (Actel) - 8

Equivalent Capacitance
CEQM = Equivalent capacitance of logic modules in pF The power dissipated by a CMOS circuit can be expressed by CEQI = Equivalent capacitance of input buffers in pF the Equation 1. CEQO = Equivalent capacitance of output buffers in pF Power (uW) = CEQ * VCC2 * F (1) CEQCR = Equivalent capacitance of routed array clock in Where: pF CEQ is the equivalent capacitance expressed in pF. CL = Output lead capacitance in pF VCC is the power supply in volts. fm = Average logic module switching rate in MHz

F is the switching frequency in MHz. fn = Average input buffer switching rate in MHz Equivalent capacitance is calculated by measuring ICCactive fp = Average output buffer switching rate in MHz at a specified frequency and voltage for each circuit f component of interest. Measurements have been made over a q1 = Average first routed array clock rate in MHz (All families) range of frequencies at a fixed value of VCC. Equivalent capacitance is frequency independent so that the results may
Fixed Capacitance Values for Actel FPGAs
be used over a wide range of operating conditions. Equivalent
(pF)
capacitance values are shown below. r1
CEQ Values for Actel FPGAs
Device Type routed_Clk1 A1010B 41.4 A10V10B A1010B A10V20B A1020B A1020B 68.6 Modules (CEQM) 3.2 3.7 A10V10B 40 Input Buffers (CEQI) 10.9 22.1 A10V20B 65 Output Buffers (CEQO) 11.6 31.2
Determining Average Switching Frequency
Routed Array Clock Buffer To determine the switching frequency for a design, you must Loads (CEQCR) 4.1 4.6 have a detailed understanding of the data input values to the circuit. The following guidelines are meant to represent To calculate the active power dissipated from the complete worst-case scenarios so that they can be generally used to design, the switching frequency of each part of the logic must predict the upper limits of power dissipation. These be known. Equation 2 shows a piece-wise linear summation guidelines are as follows: over all components. Logic Modules (m) 90% of modules Power = V 2 CC * [(m * CEQM * fm)modules + Inputs switching (n) #inputs/4 (n * CEQI* fn)inputs + (p * (CEQO+ CL) * fp)outputs + Outputs switching (p) #outputs/4 0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r First routed array clock loads (q1) 40% of modules 1 * fq1)routed_Clk1] (2) Load capacitance (C Where: L) 35 pF Average logic module switching rate (f m = Number of logic modules switching at fm m) F/10 Average input switching rate (f n = Number of input buffers switching at fn n) F/5 Average output switching rate (f p = Number of output buffers switching at fp p) F/10 Average first routed array clock rate F q1 = Number of clock loads on the first routed array (f clock (All families) q1) r1 = Fixed capacitance due to first routed array clock (All families)
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Document Outline ACT™ 1 Series FPGAs Features Description Product Family Profile The Designer and Designer Advantage™ Systems ACT 1 Device Structure The ACT 1 Logic Module I/O Buffers Device Organization Probe Pin ACT 1 Array Performance Temperature and Voltage Effects Logic Module Size Ordering Information Product Plan Device Resources Pin Description Absolute Maximum Ratings1 Free air temperature range Recommended Operating Conditions Electrical Specifications (5V) Electrical Specifications (3.3V) Package Thermal Characteristics General Power Equation Static Power Component Active Power Component Equivalent Capacitance CEQ Values for Actel FPGAs Fixed Capacitance Values for Actel FPGAs (pF) Determining Average Switching Frequency Functional Timing Tests Output Buffer Performance Derating (5V) Output Buffer Performance Derating (3.3V) ACT 1 Timing Module* Predictable Performance: Tight Delay Distributions... Timing Characteristics Critical Nets and Typical Nets Long Tracks Timing Derating Timing Derating Factor (Temperature and Voltage) Timing Derating Factor for Designs at Typical Temp... Temperature and Voltage Derating Factors (normaliz... Temperature and Voltage Derating Factors (normaliz... Junction Temperature and Voltage Derating Curves (... Parameter Measurement Output Buffer Delays AC Test Loads Input Buffer Delays Module Delays Sequential Timing Characteristics Flip-Flops and Latches ACT 1 Timing Characteristics (Worst-Case Commercial Conditions, VCC = 4.75 V,T... ACT 1 Timing Characteristics (continued) (Worst-Case Commercial Conditions) ACT 1 Timing Characteristics (continued) (Worst-Case Commercial Conditions) Package Pin Assignments 44-Pin PLCC 68-Pin PLCC Package Pin Assignments (continued) 84-Pin PLCC Package Pin Assignments (continued) 100-Pin PQFP Package Pin Assignments (continued) 80-Pin VQFP Package Pin Assignments (continued) 84-Pin CPGA Package Pin Assignments (continued) 84-Pin CQFP