Search for: "frequency meter"
Search results: 476
.. Zener diode D 7 shifts the voltage at IC 1 ’s feedback input terminal into its linear range (0 to 1 V). To avoid high-frequency instability in the compensation loop, keep connections to ceramic capacitor C 4 as short as possible. ...
.. to a separate 47 pF capacitor to compensate for possible noise from interconnecting traces. A relatively low switching frequency, around 150 kHz, and a relatively high phase inductance of 10 uH are used to reduce switching losses at ...
.. Q 1 , and V IN is the input voltage. The duty cycle is equal to where T ON is the on-time of Q 1 and T S is the switching-frequency period. Figure 1. In the basic buck-regulator circuit, current flows continuously through inductor L 1 ...
.. LED visual indication of a low-battery condition. This LBO (low-battery-indicator) is achieved by pulsing the LED at a low frequency and low duty cycle. The circuit accomplishes this without draining excessive battery current that can ...
.. to the feedback gain to stabilize the circuit and maximize the system bandwidth. The following equation calculates the pole frequency, f P : The following equation determines the zero frequency, f Z : Figure 3 shows the amplifier's ...
.. the laser diode's forward-voltage drop. The complete circuit also includes R4 and C1 for loop stability, with rolloff frequency f: One subtlety of providing a setpoint to the non-inverting input of an op amp (as opposed to summing ...
.. approximately 1-to-1. So, the duty cycle is approximately 50%, which means that the MOSFET conducts for half the switching-frequency period. Materials on the topic Datasheet ON Semiconductor MC33166
.. C, R 2 , and R 3 are the timing components for IC 1 . With R 2 = R 3 = 10 kΩ and C = 0.1 µF, the measured clock frequency is approximately 360 Hz. Figure 1. This simple timing circuit ensures that a controller’s ...
.. proxy for the circuit’s INL (integral non-linearity) performance. At an ADC sample rate of 800 kHz, we use an input frequency of about 100 Hz (slightly adjusted to ensure coherent sampling, alleviating FFT numerical limitations). ...
.. that are successive in time and have accurate duty cycles of 33.3%. You can determine the upper limit of the clock frequency from an assumption of the gate output, which changes after a low-to-high transition of the clock. This ...