Datasheet AD8330 (Analog Devices) - 4

ManufacturerAnalog Devices
DescriptionLow Cost, DC to 150 MHz, Variable Gain Amplifier
Pages / Page32 / 4 — AD8330. Data Sheet. Parameter. Conditions. Min. Typ. Max. Unit
RevisionH
File Format / SizePDF / 1.4 Mb
Document LanguageEnglish

AD8330. Data Sheet. Parameter. Conditions. Min. Typ. Max. Unit

AD8330 Data Sheet Parameter Conditions Min Typ Max Unit

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AD8330 Data Sheet Parameter Conditions Min Typ Max Unit
LINEAR GAIN INTERFACE Pin VMAG, Pin CMGN Peak Output Scaling, Gain vs. VMAG See the Circuit Description section 3.8 4.0 4.2 V/V Gain Multiplication Factor vs. VMAG Gain is nominal when VMAG = 0.5 V ×2 Usable Input Range 0 5 V Default Voltage VMAG O/C 0.48 0.5 0.52 V Incremental Resistance 4 kΩ Bandwidth For VMAG ≥ 0.1 V 150 MHz CHIP ENABLE Pin ENBL Logic Voltage for Full Shutdown 0.5 V Logic Voltage for Hibernate Mode Output pins remain at CNTR 1.3 1.5 1.7 V Logic Voltage for Full Operation 2.3 V Current in Full Shutdown 20 100 μA Current in Hibernate Mode 1.5 mA Minimum Time Delay3 1.7 μs POWER SUPPLY VPSI, VPOS, VPSO, COMM, and CMOP pins Supply Voltage 2.7 6 V Quiescent Current VDBS = 0.75 V 20 27 mA 1 The use of an input common-mode voltage significantly different from the internally set value is not recommended due to its effect on noise performance. See Figure 56. 2 See the Typical Performance Characteristics section for more detailed information on distortion in a variety of operating conditions. 3 For minimum sized coupling capacitors. Rev. G | Page 4 of 32 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Circuit Description Overall Structure Normal Operating Conditions Linear-in-dB Gain Control (VDBS) Inversion of the Gain Slope Gain Magnitude Control (VMAG) Two Classes of Variable Gain Amplifiers Amplitude/Phase Response Noise, Input Capacity, and Dynamic Range Dynamic Range Input Common-Mode Range and Rejection Ratio Output Noise and Peak Swing Offset Compensation Effects of Loading on Gain and AC Response Gain Errors Due to On-Chip Resistor Tolerances Output (Input) Common-Mode Control Using the AD8330 Gain and Swing Adjustments When Loaded Input Coupling DC-Coupled Signal Path Using Single-Sided Sources and Loads Pulse Operation Preserving Absolute Gain Calculation of Noise Figure Noise as a Function of VDBS Distortion Considerations P1dB and V1dB Applications Information ADC Driving Simple AGC Amplifier Wide Range True RMS Voltmeter Evaluation Board General Description Basic Operation Options Measurement Setup AD8330-EVALZ Board Design Outline Dimensions Ordering Guide
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