Datasheet Texas Instruments SN74LVTH273DWR

3.3-V ABT Octal D-Type Flip-Flops With Clear 20-SOIC -40 to 85

Datasheets

PDF, 1.2 Mb, Revision: M, File published: Oct 13, 2003

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Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	No

3-State Output	No
Bits	8
F @ Nom Voltage(Max)	160 Mhz
ICC @ Nom Voltage(Max)	5 mA
Operating Temperature Range	-40 to 85 C
Output Drive (IOL/IOH)(Max)	64/-32 mA
Package Group	SOIC
Package Size: mm2:W x L	20SOIC: 132 mm2: 10.3 x 12.8(SOIC) PKG
Rating	Catalog
Schmitt Trigger	No
Technology Family	LVT
VCC(Max)	3.6 V
VCC(Min)	2.7 V
Voltage(Nom)	3.3 V
tpd @ Nom Voltage(Max)	4.9 ns

RoHS

Compliant

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LVT Family Characteristics (Rev. A)
PDF, 98 Kb, Revision: A, File published: Mar 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
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LVT-to-LVTH Conversion
PDF, 84 Kb, File published: Dec 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
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Bus-Hold Circuit
PDF, 418 Kb, File published: Feb 5, 2001
When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

Series: SN74LVTH273 (16)