Datasheet Texas Instruments SN74HC112N3
| Manufacturer | Texas Instruments |
| Series | SN74HC112 |
| Part Number | SN74HC112N3 |
Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset 16-PDIP -40 to 85
Datasheets
SN54HC112, SN74HC112 datasheet
PDF, 598 Kb, Revision: F, File published: Sep 26, 2003
Extract from the document
Status
| Lifecycle Status | Obsolete (Manufacturer has discontinued the production of the device) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 16 |
| Package Type | N |
| Industry STD Term | PDIP |
| JEDEC Code | R-PDIP-T |
| Width (mm) | 6.35 |
| Length (mm) | 19.3 |
| Thickness (mm) | 3.9 |
| Pitch (mm) | 2.54 |
| Max Height (mm) | 5.08 |
| Mechanical Data | Download |
Parametrics
| Approx. Price (US$) | 0.12 | 1ku |
| Bits(#) | 2 |
| F @ Nom Voltage(Max)(Mhz) | 70 |
| ICC @ Nom Voltage(Max)(mA) | 0.04 |
| Input Type | LVTTL/CMOS |
| Output Drive (IOL/IOH)(Max)(mA) | -4/4 |
| Output Type | CMOS |
| Package Group | PDIP |
| Package Size: mm2:W x L (PKG) | See datasheet (PDIP) |
| Rating | Catalog |
| Schmitt Trigger | No |
| Technology Family | HC |
| VCC(Max)(V) | 6 |
| VCC(Min)(V) | 2 |
| Voltage(Nom)(V) | 3.3 5 |
| tpd @ Nom Voltage(Max)(ns) | 41 |
Eco Plan
| RoHS | Not Compliant |
| Pb Free | No |
Application Notes
- HCMOS Design Considerations (Rev. A)PDF, 207 Kb, Revision: A, File published: Sep 9, 2002
This document describes a potential problem designers may encounter when using high-speed CMOS (HC) logic devices. There also is a broad range of CMOS-system to non-CMOS-system interfaces that need to be considered. The design engineer inevitably encounters these interfaces. Key considerations for handling these interfaces are also discussed in this book.
Model Line
Series: SN74HC112 (9)
Manufacturer's Classification
- Semiconductors > Logic > Flip-Flop/Latch/Register > J-K Flip-Flop