Datasheet Texas Instruments ADS5242

ManufacturerTexas Instruments
SeriesADS5242
Datasheet Texas Instruments ADS5242

Quad-Channel, 12-Bit, 65-MSPS Analog-to-Digital Converter (ADC)

Datasheets

4-Channel, 12-Bit, 65MSPS Analog-to-Digital Converter with Serial LVDS Interface datasheet
PDF, 1.6 Mb, Revision: C, File published: Oct 19, 2005
Extract from the document

Prices

Status

ADS5242IPAPADS5242IPAPT
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNo

Packaging

ADS5242IPAPADS5242IPAPT
N12
Pin6464
Package TypePAPPAP
Industry STD TermHTQFPHTQFP
JEDEC CodeS-PQFP-GS-PQFP-G
Package QTY160250
CarrierJEDEC TRAY (10+1)SMALL T&R
Device MarkingADS5242IPAPADS5242IPAP
Width (mm)1010
Length (mm)1010
Thickness (mm)11
Pitch (mm).5.5
Max Height (mm)1.21.2
Mechanical DataDownloadDownload

Parametrics

Parameters / ModelsADS5242IPAP
ADS5242IPAP
ADS5242IPAPT
ADS5242IPAPT
# Input Channels44
Analog Input BW, MHz300300
ArchitecturePipelinePipeline
DNL(Max), +/-LSB11
DNL(Typ), +/-LSB0.310.31
ENOB, Bits11.511.5
INL(Max), +/-LSB2.52.5
INL(Typ), +/-LSB0.410.41
Input BufferNoNo
Input Range, Vp-p22
InterfaceParallel LVDSParallel LVDS
Operating Temperature Range, C-40 to 85-40 to 85
Package GroupHTQFPHTQFP
Package Size: mm2:W x L, PKG64HTQFP: 144 mm2: 12 x 12(HTQFP)64HTQFP: 144 mm2: 12 x 12(HTQFP)
Power Consumption(Typ), mW599599
RatingCatalogCatalog
Reference ModeExt,IntExt,Int
Resolution, Bits1212
SFDR, dB8585
SINAD, dB70.870.8
SNR, dB7171
Sample Rate(Max), MSPS6565

Eco Plan

ADS5242IPAPADS5242IPAPT
RoHSCompliantCompliant

Application Notes

  • Interfacing High-Speed LVDS Outputs of the ADS527x/ADS524x
    PDF, 67 Kb, File published: Feb 23, 2005
    The ADS527x and ADS524x families of devices are high-performance octal/quad channel analog-to-digital converters, ideal for the highest system density. Serial low voltage differential signaling (LVDS) outputs reduce the number of I/O interfaces required, power and overall package size. These device families are rated to work from sampling rates of 20MSPS to 70MSPS, corresponding to data rates of 2
  • CDCE62005 as Clock Solution for High-Speed ADCs
    PDF, 805 Kb, File published: Sep 4, 2008
    TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
  • Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)
    PDF, 2.0 Mb, Revision: A, File published: May 22, 2015
  • Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)
    PDF, 1.2 Mb, Revision: A, File published: Jul 19, 2013
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, File published: Apr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, Revision: A, File published: Sep 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, File published: Jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, File published: Jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, Revision: A, File published: Apr 16, 2015
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, Revision: B, File published: Oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, Revision: A, File published: May 18, 2015

Model Line

Series: ADS5242 (2)

Manufacturer's Classification

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)