Datasheet Texas Instruments ADS5422
Manufacturer | Texas Instruments |
Series | ADS5422 |
14-Bit, 62-MSPS Analog-to-Digital Converter (ADC)
Datasheets
14-Bit, 62MSPS Sampling Analog-To-Digital Converter datasheet
PDF, 994 Kb, Revision: D, File published: Jun 22, 2005
Extract from the document
Prices
Status
ADS5422Y/250 | |
---|---|
Lifecycle Status | Active (Recommended for new designs) |
Manufacture's Sample Availability | No |
Packaging
ADS5422Y/250 | |
---|---|
N | 1 |
Pin | 64 |
Package Type | PM |
Industry STD Term | LQFP |
JEDEC Code | S-PQFP-G |
Package QTY | 250 |
Carrier | SMALL T&R |
Device Marking | ADS5422Y |
Width (mm) | 10 |
Length (mm) | 10 |
Thickness (mm) | 1.4 |
Pitch (mm) | .5 |
Max Height (mm) | 1.6 |
Mechanical Data | Download |
Parametrics
Parameters / Models | ADS5422Y/250 |
---|---|
# Input Channels | 1 |
Analog Input BW, MHz | 300 |
Architecture | Pipeline |
DNL(Max), +/-LSB | 1 |
DNL(Typ), +/-LSB | 0.65 |
ENOB, Bits | 11.7 |
INL(Typ), +/-LSB | 4 |
Input Buffer | No |
Input Range, Vp-p | 2,4 |
Interface | Parallel LVDS |
Operating Temperature Range, C | -40 to 85 |
Package Group | LQFP |
Package Size: mm2:W x L, PKG | 64LQFP: 144 mm2: 12 x 12(LQFP) |
Power Consumption(Typ), mW | 1200 |
Rating | Catalog |
Reference Mode | Ext,Int |
Resolution, Bits | 14 |
SFDR, dB | 85 |
SINAD, dB | 72 |
SNR, dB | 72 |
Sample Rate(Max), MSPS | 62 |
Eco Plan
ADS5422Y/250 | |
---|---|
RoHS | Compliant |
Application Notes
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This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference. - Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)PDF, 327 Kb, Revision: A, File published: Sep 10, 2010
This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir - Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)PDF, 1.2 Mb, Revision: A, File published: Jul 19, 2013
- CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Kb, File published: Jun 8, 2008
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- Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Mb, File published: Jun 2, 2008
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- High-Speed Analog-to-Digital Converter BasicsPDF, 1.1 Mb, File published: Jan 11, 2012
The goal of this document is to introduce a wide range of theories and topics that are relevant tohigh-speed analog-to-digital converters (ADC). This document provides details on sampling theorydata-sheet specifications ADC selection criteria and evaluation methods clock jitter and other commonsystem-level concerns. In addition some end-users will want to extend the performance capabil - Smart Selection of ADC/DAC Enables Better Design of Software-Defined RadioPDF, 376 Kb, File published: Apr 28, 2009
This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
Model Line
Series: ADS5422 (1)
Manufacturer's Classification
- Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)