Datasheet Texas Instruments ADS61JB23
| Manufacturer | Texas Instruments |
| Series | ADS61JB23 |
12-Bit, 80-MSPS Analog-to-Digital Converter (ADC)
Datasheets
12-Bit Input-Buffered 80 MSPS ADC with JESD204A Output Interface datasheet
PDF, 1.3 Mb, File published: Dec 1, 2012
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Prices
Status
| ADS61JB23IRHAR | ADS61JB23IRHAT | |
|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes | No |
Packaging
| ADS61JB23IRHAR | ADS61JB23IRHAT | |
|---|---|---|
| N | 1 | 2 |
| Pin | 40 | 40 |
| Package Type | RHA | RHA |
| Industry STD Term | VQFN | VQFN |
| JEDEC Code | S-PQFP-N | S-PQFP-N |
| Package QTY | 2500 | 250 |
| Carrier | LARGE T&R | SMALL T&R |
| Device Marking | 61JB23 | 61JB23 |
| Width (mm) | 6 | 6 |
| Length (mm) | 6 | 6 |
| Thickness (mm) | .9 | .9 |
| Pitch (mm) | .5 | .5 |
| Max Height (mm) | 1 | 1 |
| Mechanical Data | Download | Download |
Parametrics
| Parameters / Models | ADS61JB23IRHAR | ADS61JB23IRHAT |
|---|---|---|
| # Input Channels | 1 | 1 |
| Analog Input BW, MHz | 480 | 480 |
| Architecture | Pipeline | Pipeline |
| DNL(Max), +/-LSB | 0.8 | 0.8 |
| DNL(Typ), +/-LSB | 0.3 | 0.3 |
| ENOB, Bits | 11.5 | 11.5 |
| INL(Max), +/-LSB | 1.5 | 1.5 |
| INL(Typ), +/-LSB | 0.7 | 0.7 |
| Input Buffer | Yes | Yes |
| Input Range, Vp-p | 2 | 2 |
| Interface | JESD204A | JESD204A |
| Operating Temperature Range, C | -40 to 85 | -40 to 85 |
| Package Group | VQFN | VQFN |
| Package Size: mm2:W x L, PKG | 40VQFN: 36 mm2: 6 x 6(VQFN) | 40VQFN: 36 mm2: 6 x 6(VQFN) |
| Power Consumption(Typ), mW | 440 | 440 |
| Rating | Catalog | Catalog |
| Reference Mode | Ext,Int | Ext,Int |
| Resolution, Bits | 12 | 12 |
| SFDR, dB | 80 | 80 |
| SINAD, dB | 71.2 | 71.2 |
| SNR, dB | 71.7 | 71.7 |
| Sample Rate(Max), MSPS | 80 | 80 |
Eco Plan
| ADS61JB23IRHAR | ADS61JB23IRHAT | |
|---|---|---|
| RoHS | Compliant | Compliant |
Application Notes
- Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)PDF, 1.2 Mb, Revision: A, File published: Jul 19, 2013
- Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)PDF, 2.0 Mb, Revision: A, File published: May 22, 2015
- Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)PDF, 69 Kb, Revision: A, File published: May 18, 2015
- A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)PDF, 425 Kb, Revision: B, File published: Oct 9, 2011
This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference. - Principles of Data Acquisition and Conversion (Rev. A)PDF, 132 Kb, Revision: A, File published: Apr 16, 2015
Model Line
Series: ADS61JB23 (2)
Manufacturer's Classification
- Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)
