Datasheet Texas Instruments ADS7949

ManufacturerTexas Instruments
SeriesADS7949
Datasheet Texas Instruments ADS7949

8-Bit, 2 MSPS, Dual Channel, Pseudo-differential, uPower Serial SAR ADC

Datasheets

12/10/8-Bit, 2MSPS, Dual-Ch, Unipolar, Pseudo-Diff, Ultralow-Power SAR ADCs datasheet
PDF, 874 Kb, File published: Sep 9, 2010
Extract from the document

Prices

Status

ADS7949SRTERADS7949SRTET
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityYesNo

Packaging

ADS7949SRTERADS7949SRTET
N12
Pin1616
Package TypeRTERTE
Industry STD TermWQFNWQFN
JEDEC CodeS-PQFP-NS-PQFP-N
Package QTY3000250
CarrierLARGE T&RSMALL T&R
Device Marking79497949
Width (mm)33
Length (mm)33
Thickness (mm).75.75
Pitch (mm).5.5
Max Height (mm).8.8
Mechanical DataDownloadDownload

Parametrics

Parameters / ModelsADS7949SRTER
ADS7949SRTER
ADS7949SRTET
ADS7949SRTET
# Input Channels22
Analog Voltage AVDD(Max), V5.55.5
Analog Voltage AVDD(Min), V2.72.7
ArchitectureSARSAR
Digital Supply(Max), V5.55.5
Digital Supply(Min), V1.651.65
INL(Max), +/-LSB0.30.3
Input Range(Max), V5.55.5
Input TypePseudo-Differential,Single-EndedPseudo-Differential,Single-Ended
Integrated FeaturesN/AN/A
InterfaceSPISPI
Multi-Channel ConfigurationMultiplexedMultiplexed
Operating Temperature Range, C-40 to 125-40 to 125
Package GroupWQFNWQFN
Package Size: mm2:W x L, PKG16WQFN: 9 mm2: 3 x 3(WQFN)16WQFN: 9 mm2: 3 x 3(WQFN)
Power Consumption(Typ), mW7.57.5
RatingCatalogCatalog
Reference ModeExtExt
Resolution, Bits88
SINAD, dB4949
SNR, dB4949
Sample Rate (max), SPS2MSPS2MSPS
Sample Rate(Max), MSPS22
THD(Typ), dB-80-80

Eco Plan

ADS7949SRTERADS7949SRTET
RoHSCompliantCompliant

Application Notes

  • Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)
    PDF, 227 Kb, Revision: A, File published: Nov 10, 2010
    This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different
  • Determining Minimum Acquisition Times for SAR ADCs, part 2
    PDF, 215 Kb, File published: Mar 17, 2011
    The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to
  • Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, Revision: A, File published: May 18, 2015
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, Revision: B, File published: Oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, Revision: A, File published: Apr 16, 2015

Model Line

Series: ADS7949 (2)

Manufacturer's Classification

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> Precision ADCs (<=10MSPS)
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