Datasheet Texas Instruments CD74HC75PWT
| Manufacturer | Texas Instruments |
| Series | CD74HC75 |
| Part Number | CD74HC75PWT |
High Speed CMOS Logic Dual 2-Bit Bistable Transparent Latches 16-TSSOP -55 to 125
Datasheets
CD54HC75, CD74HC75, CD54HCT75, CD74HCT75 datasheet
PDF, 694 Kb, Revision: F, File published: Oct 13, 2003
Extract from the document
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 16 |
| Package Type | PW |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 250 |
| Carrier | SMALL T&R |
| Device Marking | HJ75 |
| Width (mm) | 4.4 |
| Length (mm) | 5 |
| Thickness (mm) | 1 |
| Pitch (mm) | .65 |
| Max Height (mm) | 1.2 |
| Mechanical Data | Download |
Parametrics
| 3-State Output | No |
| Bits | 4 |
| F @ Nom Voltage(Max) | 28 Mhz |
| ICC @ Nom Voltage(Max) | 0.04 mA |
| Operating Temperature Range | -55 to 125 C |
| Output Drive (IOL/IOH)(Max) | 5.2/-5.2 mA |
| Package Group | TSSOP |
| Package Size: mm2:W x L | 16TSSOP: 32 mm2: 6.4 x 5(TSSOP) PKG |
| Rating | Catalog |
| Schmitt Trigger | No |
| Technology Family | HC |
| VCC(Max) | 6 V |
| VCC(Min) | 2 V |
| Voltage(Nom) | 6 V |
| tpd @ Nom Voltage(Max) | 24 ns |
Eco Plan
| RoHS | Compliant |
Application Notes
- Power-Up Behavior of Clocked Devices (Rev. A)PDF, 34 Kb, Revision: A, File published: Feb 6, 2015
- SN54/74HCT CMOS Logic Family Applications and RestrictionsPDF, 102 Kb, File published: May 1, 1996
The TI SN54/74HCT family of CMOS devices is a subgroup of the SN74HC series with the HCT circuitry modified to meet the interfacing requirements of TTL outputs to high-speed CMOS inputs. The HCT devices can be driven by the TTL circuits directly without additional components. This document describes the TTL/HC interface the operating voltages circuit noise and power consumption. A Bergeron anal
Model Line
Series: CD74HC75 (11)
Manufacturer's Classification
- Semiconductors > Logic > Flip-Flop/Latch/Register > Other Latch