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Datasheet Texas Instruments CDC2510

Datasheet Texas Instruments CDC2510

ManufacturerTexas Instruments
SeriesCDC2510

3.3-V Phase-Lock Loop Clock Driver

Datasheets

  • Download » Datasheet PDF, 608 Kb, Revision: B, File published: Dec 2, 2004
    CDC2510: 3.3-V Phase-Lock Loop Clock Driver datasheet
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    SCAS597B -DECEMBER 1997 -REVISED DECEMBER 2004 D Use CDCVF2510A as a Replacement for
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    (TOP VIEW) this Device
    Phase-Lock Loop Clock Distribution for
    Synchronous DRAM Applications
    Distributes One Clock Input to One Bank of
    Ten Outputs
    Single Output Enable Terminal Controls All
    Ten Outputs
    External Feedback (FBIN) Pin Is Used to
    Synchronize the Outputs to the Clock Input
    On-Chip Series Damping Resistors ...

Prices

Family: CDC2510

Status

CDC2510PWRCDC2510PWRG4
Lifecycle StatusNRND (Not recommended for new designs)NRND (Not recommended for new designs)
Manufacture's Sample AvailabilityNoNo

Packaging

CDC2510PWRCDC2510PWRG4
Pin2424
Package TypePWPW
Industry STD TermTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-G
Package QTY20002000
CarrierLARGE T&RLARGE T&R
Device MarkingCK2510CK2510
Width (mm)4.44.4
Length (mm)7.87.8
Thickness (mm)11
Pitch (mm).65.65
Max Height (mm)1.21.2
Mechanical DataDownload »Download »

Eco Plan

CDC2510PWRCDC2510PWRG4
RoHSCompliantCompliant

Application Notes

  • Download » Application Notes PDF, 65 Kb, File published: Jan 8, 1999
    Understanding the Differences Between CDC2509x/10x Devices
    This application note provides information concerning the various revisions of the TI CDC2509/10 family of devices. In addition, it will assist designers with new and existing designs. Phase error information, both slope and absolute value, is provided to assist in the tuning process. Furthermore, a table summarizes important parameters for choosing the correct PLL. The table contains capacitance
  • Download » Application Notes PDF, 109 Kb, Revision: A, File published: Sep 23, 1998
    High Speed Clock Distribution Design Techniques for CDC 509/516/2509/2510/2516 (Rev. A)
    The memory bandwidth of high performance microprocessors is increasing at a rapid rate and the future memory bandwidth requirements are expected to keep increasing. The bandwidth requirements of RAM will be satisfied in the near term by using Synchronous DRAM. The need to drive multiple DRAM chips at high speeds with low skew necessitates the use of clock distribution devices with Phase Locked Loo

Moldel Line

Series: CDC2510 (2)

Manufacturer's Classification

  • Semiconductors> Clock and Timing> Clock Buffers> Zero Delay Buffers

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