Datasheet Texas Instruments CDCE706
| Manufacturer | Texas Instruments |
| Series | CDCE706 |
Programmable 3-PLL Clock Synthesizer / Multiplier / Divider
Datasheets
Programmable 3-PLL Clock Synthesizer / Multiplier / Divider datasheet
PDF, 1.6 Mb, Revision: I, File published: Feb 7, 2008
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Prices
Status
| CDCE706PW | CDCE706PWG4 | CDCE706PWR | CDCE706PWRG4 | |
|---|---|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No | No | Yes | Yes |
Packaging
| CDCE706PW | CDCE706PWG4 | CDCE706PWR | CDCE706PWRG4 | |
|---|---|---|---|---|
| N | 1 | 2 | 3 | 4 |
| Pin | 20 | 20 | 20 | 20 |
| Package Type | PW | PW | PW | PW |
| Industry STD Term | TSSOP | TSSOP | TSSOP | TSSOP |
| JEDEC Code | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G |
| Package QTY | 70 | 70 | 2000 | 2000 |
| Carrier | TUBE | TUBE | LARGE T&R | LARGE T&R |
| Device Marking | CDCE706 | CDCE706 | CDCE706 | CDCE706 |
| Width (mm) | 4.4 | 4.4 | 4.4 | 4.4 |
| Length (mm) | 6.5 | 6.5 | 6.5 | 6.5 |
| Thickness (mm) | 1 | 1 | 1 | 1 |
| Pitch (mm) | .65 | .65 | .65 | .65 |
| Max Height (mm) | 1.2 | 1.2 | 1.2 | 1.2 |
| Mechanical Data | Download | Download | Download | Download |
Parametrics
| Parameters / Models | CDCE706PW | CDCE706PWG4 | CDCE706PWR | CDCE706PWRG4 |
|---|---|---|---|---|
| Input Level | Crystal,LVCMOS,Differential | Crystal,LVCMOS,Differential | Crystal,LVCMOS,Differential | Crystal,LVCMOS,Differential |
| Number of Outputs | 6 | 6 | 6 | 6 |
| Operating Temperature Range, C | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 |
| Output Frequency(Max), MHz | 300 | 300 | 300 | 300 |
| Output Level | LVCMOS | LVCMOS | LVCMOS | LVCMOS |
| Package Group | TSSOP | TSSOP | TSSOP | TSSOP |
| Package Size: mm2:W x L, PKG | 20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP) | 20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP) | 20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP) | 20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP) |
| Programmability | EEPROM | EEPROM | EEPROM | EEPROM |
| Special Features | Integrated EEPROM,Pin Programming,SMBus,Spread Spectrum Clocking (SSC) | Integrated EEPROM,Pin Programming,SMBus,Spread Spectrum Clocking (SSC) | Integrated EEPROM,Pin Programming,SMBus,Spread Spectrum Clocking (SSC) | Integrated EEPROM,Pin Programming,SMBus,Spread Spectrum Clocking (SSC) |
| VCC Core, V | 3.3 | 3.3 | 3.3 | 3.3 |
| VCC Out, V | 3.3 | 3.3 | 3.3 | 3.3 |
Eco Plan
| CDCE706PW | CDCE706PWG4 | CDCE706PWR | CDCE706PWRG4 | |
|---|---|---|---|---|
| RoHS | Compliant | Compliant | Compliant | Compliant |
Application Notes
- Recommended Terminations for the Differential Inputs of CDCE906/CDCE706PDF, 84 Kb, File published: Aug 10, 2006
This application report describes how differential signals (LVDS, LVPECL, and HSTL) can be connected to CDCE706/CDCE906 differential inputs directly. The wide common-mode voltage and smaller swing required make the devices so versatile that they can receive any signal without any complicated coupling and biasing circuits. - CDCx706/x906 Termination and Signal Integrity Guidelines (Rev. A)PDF, 155 Kb, Revision: A, File published: Nov 28, 2007
This application report shows and evaluates different schemes for the CDCE706, CDCE906, CDC706, and CDC906. Guidelines for optimizing the series termination are discussed. Additionally, this report describes how the CDCx706/x906 family can be used to drive 1.8-V clock inputs. - High Speed Layout Guidelines (Rev. A)PDF, 762 Kb, Revision: A, File published: Aug 8, 2017
Thisapplicationreportaddresseshigh-speedsignals,suchas clocksignalsand theirrouting,and givesdesignersa reviewof the importantcoherences.Withsomesimplerules,electromagneticinterferenceproblemscan be minimizedwithoutusingcomplicatedformulasand expensivesimulationtools.Section1givesa shortintroductionto theory,whileSection - Clock Recommendations for the DM643x EVMPDF, 121 Kb, File published: Nov 29, 2006
The DM643x evaluation module (EVM) requires several clock frequencies to run the system properly. The current clocking proposal of the low-cost EVM consists of the VCXO chip PI6CX100-27W, the PLL chip PLL1705, several bus drivers, and a few oscillaors and crystals. This application report discusses several optimized clocking proposals with the Texas Instruments new clock drivers and recommends a m - Troubleshooting I2C Bus ProtocolPDF, 184 Kb, File published: Oct 19, 2009
When using the I2Cв„ў bus protocol, the designer must ensure that the hardware complies with the I2C standard. This application report describes the I2C protocol and provides guidelines on debugging a missing acknowledgment, selecting the pullup resistors, or meeting the maximum capacitance load of an I2C bus. A conflict occurs if devices sharing the I2C bus have the same slave address. This
Model Line
Series: CDCE706 (4)
Manufacturer's Classification
- Semiconductors> Clock and Timing> Clock Generators> General Purpose
