Datasheet Texas Instruments CDCEL913PWR
| Manufacturer | Texas Instruments |
| Series | CDCEL913 |
| Part Number | CDCEL913PWR |
Programmable 1-PLL VCXO Clock Synthesizer with 1.8-V LVCMOS Outputs 14-TSSOP -40 to 85
Datasheets
CDCE(L)913: Flexible Low Power LVCMOS Clock Generator With SSC Support for EMI Reduction datasheet
PDF, 1.8 Mb, Revision: G, File published: Oct 27, 2016
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Prices
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 14 |
| Package Type | PW |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 2000 |
| Carrier | LARGE T&R |
| Device Marking | CKEL913 |
| Width (mm) | 4.4 |
| Length (mm) | 5 |
| Thickness (mm) | 1 |
| Pitch (mm) | .65 |
| Max Height (mm) | 1.2 |
| Mechanical Data | Download |
Parametrics
| Divider Ratio | Universal |
| Function | Clock Synthesizer |
| Input Level | Crystal,LVCMOS |
| Jitter-Peak to Peak(P-P) or Cycle to Cycle | 60 ps C-C |
| Number of Outputs | 3 |
| Operating Temperature Range | -40 to 85 C |
| Output Frequency(Max) | 230 MHz |
| Output Level | LVCMOS |
| Output Skew | 150 ps |
| Package Group | TSSOP |
| Package Size: mm2:W x L | 14TSSOP: 32 mm2: 6.4 x 5(TSSOP) PKG |
| Programmability | EEPROM |
| Rating | Catalog |
| Special Features | Integrated EEPROM,Multiplier/Divider,Spread Spectrum Clocking (SSC) |
| VCC | 1.8 V |
| VCC Core | 1.8 V |
| VCC Out | 1.8 V |
Eco Plan
| RoHS | Compliant |
Design Kits & Evaluation Modules
- Evaluation Modules & Boards: SN65DSI83EVM
SN65DSI83 MIPIВ® DSI to FlatLinkВ™ LVDS Bridge Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: CDCEL913PERF-EVM
CDCEL913 Performance Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: CDCE913PERF-EVM
CDCE913 Performance Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: CDCEL9XXPROGEVM
CDCE(L)949 Family EEPROM Programming Board
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: SN65DSI83Q1-EVM
MIPIВ® DSI to FlatLinkВ™ LVDS Bridge Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: SN65DSI85Q1-EVM
Dual-Channel MIPIВ® DSI to Dual-Link FlatLinkВ™ LVDS Bridge Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: SN65DSI85EVM
SN65DSI85 Dual-Channel MIPIВ® DSI to Dual-Link FlatLinkВ™ LVDS Bridge Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
Application Notes
- Clocking Recommendations for DM6446 Digital Video EVM with Sngle PLL (Rev. A)PDF, 94 Kb, Revision: A, File published: Aug 8, 2007
The DM6446 (DaVinciв„ў) Digital Video Evaluation Module (EVM) requires a number of clock frequencies to run the system properly. The current clocking proposal of this EVM consists of a VCXO chip PI6CX100-27W, a PLL chip PLL1705, several voltage level translators, and a few oscillators or crystals. This application report discusses an optimized clocking proposal with Texas Instruments new clock driv - VCXO Application Guideline for CDCE(L)9xx Family (Rev. A)PDF, 107 Kb, Revision: A, File published: Apr 23, 2012
- Practical consideration on choosing a crystal for CDCE(L)9xx familyPDF, 60 Kb, File published: Mar 24, 2008
- Usage of I2C for CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913PDF, 297 Kb, File published: Sep 23, 2009
This document presents a method to smoothly change frequency by IВІCв„ў protocol on Texas Instruments CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913 Clock Synthesizers, thus avoiding unnecessary intermediate frequencies. It also includes a code example to generate the IВІC protocol for the CDCE(L)9xx with the TMS320C645x. - Generating Low Phase-Noise Clocks for Audio Data Converters from Low FrequencyPDF, 860 Kb, File published: Mar 31, 2008
Generating a high-frequency system clock Fs (128fs to 768fs) from a low-frequency sampling clock fs (10 kHz to 200 kHz) is challenging, while attempting to maintain low phase jitter. A traditional phase-lock loop (PLL) can do the frequency translation, but the added phase jitter prevents the generated system clock signal from effectively driving high-performance audio data converters. This applica - Troubleshooting I2C Bus ProtocolPDF, 184 Kb, File published: Oct 19, 2009
When using the I2Cв„ў bus protocol, the designer must ensure that the hardware complies with the I2C standard. This application report describes the I2C protocol and provides guidelines on debugging a missing acknowledgment, selecting the pullup resistors, or meeting the maximum capacitance load of an I2C bus. A conflict occurs if devices sharing the I2C bus have the same slave address. This
Model Line
Series: CDCEL913 (4)
- CDCEL913PW CDCEL913PWG4 CDCEL913PWR CDCEL913PWRG4
Manufacturer's Classification
- Semiconductors > Clock and Timing > Clock Generators > Spread-Spectrum Clocks
