Datasheet Texas Instruments CDCV855
| Manufacturer | Texas Instruments |
| Series | CDCV855 |
1:4 DDR PLL Clock Driver
Datasheets
2.5-V Phase-Lock Loop Clock Driver datasheet
PDF, 759 Kb, Revision: A, File published: Dec 12, 2002
Extract from the document
Status
| CDCV855IPW | CDCV855IPWG4 | CDCV855IPWR | CDCV855IPWRG4 | CDCV855PW | CDCV855PWG4 | CDCV855PWR | CDCV855PWRG4 | |
|---|---|---|---|---|---|---|---|---|
| Lifecycle Status | NRND (Not recommended for new designs) | NRND (Not recommended for new designs) | NRND (Not recommended for new designs) | NRND (Not recommended for new designs) | NRND (Not recommended for new designs) | NRND (Not recommended for new designs) | NRND (Not recommended for new designs) | NRND (Not recommended for new designs) |
| Manufacture's Sample Availability | No | No | No | No | No | No | No | No |
Packaging
| CDCV855IPW | CDCV855IPWG4 | CDCV855IPWR | CDCV855IPWRG4 | CDCV855PW | CDCV855PWG4 | CDCV855PWR | CDCV855PWRG4 | |
|---|---|---|---|---|---|---|---|---|
| N | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
| Pin | 28 | 28 | 28 | 28 | 28 | 28 | 28 | 28 |
| Package Type | PW | PW | PW | PW | PW | PW | PW | PW |
| Industry STD Term | TSSOP | TSSOP | TSSOP | TSSOP | TSSOP | TSSOP | TSSOP | TSSOP |
| JEDEC Code | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G |
| Package QTY | 50 | 50 | 2000 | 2000 | 50 | 50 | 2000 | 2000 |
| Carrier | TUBE | TUBE | LARGE T&R | LARGE T&R | TUBE | TUBE | LARGE T&R | LARGE T&R |
| Device Marking | CDCV855-I | CDCV855-I | CDCV855-I | CDCV855-I | CDCV855 | CDCV855 | CDCV855 | CDCV855 |
| Width (mm) | 4.4 | 4.4 | 4.4 | 4.4 | 4.4 | 4.4 | 4.4 | 4.4 |
| Length (mm) | 9.7 | 9.7 | 9.7 | 9.7 | 9.7 | 9.7 | 9.7 | 9.7 |
| Thickness (mm) | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| Pitch (mm) | .65 | .65 | .65 | .65 | .65 | .65 | .65 | .65 |
| Max Height (mm) | 1.2 | 1.2 | 1.2 | 1.2 | 1.2 | 1.2 | 1.2 | 1.2 |
| Mechanical Data | Download | Download | Download | Download | Download | Download | Download | Download |
Eco Plan
| CDCV855IPW | CDCV855IPWG4 | CDCV855IPWR | CDCV855IPWRG4 | CDCV855PW | CDCV855PWG4 | CDCV855PWR | CDCV855PWRG4 | |
|---|---|---|---|---|---|---|---|---|
| RoHS | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant |
Application Notes
- Design Considerations for TI's CDCV857/CDCV857A/CDCV855 DRR PLL (Rev. A)PDF, 362 Kb, Revision: A, File published: Nov 20, 2005
Model Line
Series: CDCV855 (8)
Manufacturer's Classification
- Semiconductors> Clock and Timing> Clock Buffers> Zero Delay Buffers