Datasheet Texas Instruments CP3SP33SMS/NOPB

CP3SP33
www.ti.com SNOSCW5 – MAY 2013 Connectivity Processor with Cache, DSP, and Bluetooth®, USB, and Dual CAN Interfaces
Check for Samples: CP3SP33 1 Introduction
1.1 Features 123 CPU Features
– Fully static RISC processor core, capable of
operating from 0 to 96 MHz with zero
wait/hold state
– Minimum 10.4 ns instruction cycle time with
a 96-MHz internal clock frequency, based on
a 12-MHz external input
– 4K-byte, 4-way set-associative instruction
cache
– 69 independently vectored peripheral
interrupts DSP Features
– Capable of operating up to 96 MHz
– 16-bit fixed-point arithmetic, dual-MAC
architecture
– 32-bit interface to 4K-byte RAM shared with
CPU
– 32-bit external bus interface
– Bus master interface to audio peripherals
and I/O Memory
– 4K bytes CPU instruction cache …