Datasheet Texas Instruments CY54FCT373T
| Manufacturer | Texas Instruments |
| Series | CY54FCT373T |
Octal Transparent D-Type Latches with 3-State Outputs
Datasheets
8-Bit Latches datasheet
PDF, 678 Kb, Revision: B, File published: Aug 20, 2001
Extract from the document
Prices
Status
| 5962-9221701MRA | 5962-9221702MRA | 5962-9221703M2A | CY54FCT373ATDMB | |
|---|---|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No | No | No | No |
Packaging
| 5962-9221701MRA | 5962-9221702MRA | 5962-9221703M2A | CY54FCT373ATDMB | |
|---|---|---|---|---|
| N | 1 | 2 | 3 | 4 |
| Pin | 20 | 20 | 20 | 20 |
| Package Type | J | J | FK | J |
| Industry STD Term | CDIP | CDIP | LCCC | CDIP |
| JEDEC Code | R-GDIP-T | R-GDIP-T | S-CQCC-N | R-GDIP-T |
| Package QTY | 1 | 1 | 1 | 1 |
| Carrier | TUBE | TUBE | TUBE | TUBE |
| Width (mm) | 6.92 | 6.92 | 8.89 | 6.92 |
| Length (mm) | 24.2 | 24.2 | 8.89 | 24.2 |
| Thickness (mm) | 4.57 | 4.57 | 1.83 | 4.57 |
| Pitch (mm) | 2.54 | 2.54 | 1.27 | 2.54 |
| Max Height (mm) | 5.08 | 5.08 | 2.03 | 5.08 |
| Mechanical Data | Download | Download | Download | Download |
| Device Marking | 5962-9221702MR |
Parametrics
| Parameters / Models | 5962-9221701MRA | 5962-9221702MRA | 5962-9221703M2A | CY54FCT373ATDMB |
|---|---|---|---|---|
| Bits | 8 | |||
| F @ Nom Voltage(Max), Mhz | 70 | |||
| ICC @ Nom Voltage(Max), mA | 0.5 | |||
| Operating Temperature Range, C | -55 to 125 | -55 to 125 | ||
| Output Drive (IOL/IOH)(Max), mA | 24/-24 | |||
| Package Group | CDIP | CDIP | ||
| Package Size: mm2:W x L, PKG | See datasheet (CDIP) | See datasheet (CDIP) | ||
| Rating | Military | Military | ||
| Technology Family | FCT | FCT | ||
| tpd @ Nom Voltage(Max), ns | 4.2 |
Eco Plan
| 5962-9221701MRA | 5962-9221702MRA | 5962-9221703M2A | CY54FCT373ATDMB | |
|---|---|---|---|---|
| RoHS | See ti.com | See ti.com | See ti.com | See ti.com |
Application Notes
- Power-Up Behavior of Clocked Devices (Rev. A)PDF, 34 Kb, Revision: A, File published: Feb 6, 2015
- Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)PDF, 614 Kb, Revision: C, File published: Dec 2, 2015
- Semiconductor Packing Material Electrostatic Discharge (ESD) ProtectionPDF, 337 Kb, File published: Jul 8, 2004
Forty-eight-pin TSSOP components that were packaged using Texas Instruments (TI) standard packing methodology were subjected to electrical discharges between 0.5 and 20 kV as generated by an IEC ESD simulator to determine the level of ISD protection provided by the packing materials. The testing included trays tape and reel and magazines. Additional units were subjected to the same discharge - Selecting the Right Level Translation Solution (Rev. A)PDF, 313 Kb, Revision: A, File published: Jun 22, 2004
Supply voltages continue to migrate to lower nodes to support today's low-power high-performance applications. While some devices are capable of running at lower supply nodes others might not have this capability. To haveswitching compatibility between these devices the output of each driver must be compliant with the input of the receiver that it is driving. There are several level-translati - Introduction to LogicPDF, 93 Kb, File published: Apr 30, 2015
Model Line
Series: CY54FCT373T (4)
Manufacturer's Classification
- Semiconductors> Space & High Reliability> Logic Products> Flip-Flop/Latch/Registers
