Datasheet Texas Instruments DS90C363BMT/NOPB
| Manufacturer | Texas Instruments |
| Series | DS90C363B |
| Part Number | DS90C363BMT/NOPB |
+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link - 65MHz 48-TSSOP -10 to 70
Datasheets
DS90C363B 3.3V Prog LVDS Transm 18-Bit FPD Link -65 MHz datasheet
PDF, 920 Kb, Revision: F, File published: Apr 12, 2013
Extract from the document
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes |
Packaging
| Pin | 48 |
| Package Type | DGG |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 38 |
| Carrier | TUBE |
| Device Marking | DS90C363BMT |
| Width (mm) | 6.1 |
| Length (mm) | 12.5 |
| Thickness (mm) | 1.15 |
| Pitch (mm) | .5 |
| Max Height (mm) | 1.2 |
| Mechanical Data | Download |
Parametrics
| Color Depth | 18 bpp |
| Function | Transmitter |
| Input Compatibility | LVCMOS,LVTTL |
| Operating Temperature Range | -10 to 70 C |
| Output Compatibility | FPD-Link LVDS |
| Package Group | TSSOP |
| Package Size: mm2:W x L | 48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP) PKG |
| Pixel Clock Min | 18 MHz |
| Pixel Clock(Max) | 68 MHz |
| Rating | Catalog |
| Total Throughput | 1300 Mbps |
Eco Plan
| RoHS | Compliant |
Design Kits & Evaluation Modules
- Evaluation Modules & Boards: FLINK3V8BT-85
Evaluation Kit for FPD-Link Family of Serializer and Deserializer LVDS Devices
Lifecycle Status: Active (Recommended for new designs)
Application Notes
- AN-1056 STN Application Using FPD-LinkPDF, 85 Kb, File published: May 14, 2004
Application Note 1056 STN Application Using FPD-Link - TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color MapPDF, 52 Kb, File published: May 15, 2004
Application Note 1163 TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map - LVDS Display Interface (LDI) TFT Data Mapping for Interoperability w/FPD-LinkPDF, 65 Kb, File published: May 14, 2004
Application Note 1127 LVDS Display Interface (LDI) TFT Data Mapping for Interoperabil ity with FPD-Link - AN-1085 FPD-Link PCB and Interconnect Design-In GuidelinesPDF, 344 Kb, File published: May 14, 2004
Application Note 1085 FPD-Link PCB and Interconnect Design-In Guidelines - Receiver Skew Margin for Channel Link I and FPD Link I DevicesPDF, 418 Kb, File published: Jan 13, 2016
- AN-1032 An Introduction to FPD-Link (Rev. C)PDF, 185 Kb, Revision: C, File published: Aug 8, 2017
The FPD-Linkchipsetarchitecturein conjunctionwith the LVDStechnologyprovidesthe highbandwidthinterfacenecessaryfor leadingedgedisplaytechnology.The conversionfromparallelTTL to serialLVDSallowsfor a narrowinterfacebetweengraphicscontrollerand panel.A narrowerinterfacemeanslowercablecost and simplifiesthe physicalconnectionthroug
Model Line
Series: DS90C363B (3)
- DS90C363BMT DS90C363BMT/NOPB DS90C363BMTX/NOPB
Manufacturer's Classification
- Semiconductors > Interface > FPD-Link SerDes > Display SerDes