Datasheet Texas Instruments DS90CF383B
| Manufacturer | Texas Instruments |
| Series | DS90CF383B |
+3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz
Datasheets
DS90CF383B 3.3V Prog LVDS Transm 24-Bit FPD Link-65 MHz datasheet
PDF, 1.3 Mb, Revision: E, File published: Apr 17, 2013
Extract from the document
Status
| DS90CF383BMTX/NOPB | |
|---|---|
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| DS90CF383BMTX/NOPB | |
|---|---|
| N | 1 |
| Pin | 56 |
| Package Type | DGG |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 1000 |
| Carrier | LARGE T&R |
| Device Marking | DS90CF383BMT |
| Width (mm) | 6.1 |
| Length (mm) | 14 |
| Thickness (mm) | 1.15 |
| Pitch (mm) | .5 |
| Max Height (mm) | 1.2 |
| Mechanical Data | Download |
Parametrics
| Parameters / Models | DS90CF383BMTX/NOPB |
|---|---|
| Color Depth, bpp | 24 |
| Function | Transmitter |
| Input Compatibility | LVCMOS,LVTTL |
| Operating Temperature Range, C | -10 to 70 |
| Output Compatibility | FPD-Link LVDS |
| Package Group | TSSOP |
| Package Size: mm2:W x L, PKG | 56TSSOP: 113 mm2: 8.1 x 14(TSSOP) |
| Pixel Clock Min, MHz | 18 |
| Pixel Clock(Max), MHz | 68 |
| Rating | Catalog |
| Total Throughput, Mbps | 1800 |
Eco Plan
| DS90CF383BMTX/NOPB | |
|---|---|
| RoHS | Compliant |
Application Notes
- AN-1056 STN Application Using FPD-LinkPDF, 85 Kb, File published: May 14, 2004
Application Note 1056 STN Application Using FPD-Link - TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color MapPDF, 52 Kb, File published: May 15, 2004
Application Note 1163 TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map - LVDS Display Interface (LDI) TFT Data Mapping for Interoperability w/FPD-LinkPDF, 65 Kb, File published: May 14, 2004
Application Note 1127 LVDS Display Interface (LDI) TFT Data Mapping for Interoperabil ity with FPD-Link - AN-1085 FPD-Link PCB and Interconnect Design-In GuidelinesPDF, 344 Kb, File published: May 14, 2004
Application Note 1085 FPD-Link PCB and Interconnect Design-In Guidelines - Receiver Skew Margin for Channel Link I and FPD Link I DevicesPDF, 418 Kb, File published: Jan 13, 2016
- AN-1032 An Introduction to FPD-Link (Rev. C)PDF, 185 Kb, Revision: C, File published: Aug 8, 2017
The FPD-Linkchipsetarchitecturein conjunctionwith the LVDStechnologyprovidesthe highbandwidthinterfacenecessaryfor leadingedgedisplaytechnology.The conversionfromparallelTTL to serialLVDSallowsfor a narrowinterfacebetweengraphicscontrollerand panel.A narrowerinterfacemeanslowercablecost and simplifiesthe physicalconnectionthroug
Model Line
Series: DS90CF383B (1)
Manufacturer's Classification
- Semiconductors> Interface> Display & Imaging SerDes> FlatLink/FPD-Link (LVDS for LCD)