Datasheet Texas Instruments DS99R102
| Manufacturer | Texas Instruments |
| Series | DS99R102 |
3-40MHz DC-Balanced 24-Bit LVDS Deserializer
Datasheets
DS99R101/DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer datasheet
PDF, 909 Kb, Revision: D, File published: Apr 16, 2013
Extract from the document
Status
| DS99R102VS/NOPB | DS99R102VSX/NOPB | |
|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No | Yes |
Packaging
| DS99R102VS/NOPB | DS99R102VSX/NOPB | |
|---|---|---|
| N | 1 | 2 |
| Pin | 48 | 48 |
| Package Type | PFB | PFB |
| Industry STD Term | TQFP | TQFP |
| JEDEC Code | S-PQFP-G | S-PQFP-G |
| Package QTY | 250 | 1000 |
| Device Marking | VS | DS99R102 |
| Width (mm) | 7 | 7 |
| Length (mm) | 7 | 7 |
| Thickness (mm) | 1 | 1 |
| Pitch (mm) | .5 | .5 |
| Max Height (mm) | 1.2 | 1.2 |
| Mechanical Data | Download | Download |
| Carrier | LARGE T&R |
Parametrics
| Parameters / Models | DS99R102VS/NOPB | DS99R102VSX/NOPB |
|---|---|---|
| Color Depth, bpp | 18 | 18 |
| Diagnostics | - | - |
| EMI Reduction | Progressive Turn On (PTO) | Progressive Turn On (PTO) |
| Function | Deserializer | Deserializer |
| Input Compatibility | FPD-Link II LVDS | FPD-Link II LVDS |
| Operating Temperature Range, C | 0 to 70 | 0 to 70 |
| Output Compatibility | LVCMOS | LVCMOS |
| Package Group | TQFP | TQFP |
| Package Size: mm2:W x L, PKG | 48TQFP: 81 mm2: 9 x 9(TQFP) | 48TQFP: 81 mm2: 9 x 9(TQFP) |
| Pixel Clock Min, MHz | 3 | 3 |
| Pixel Clock(Max), MHz | 40 | 40 |
| Rating | Catalog | Catalog |
| Signal Conditioning | - | - |
| Special Features | - | - |
| Total Throughput, Mbps | 960 | 960 |
Eco Plan
| DS99R102VS/NOPB | DS99R102VSX/NOPB | |
|---|---|---|
| RoHS | Compliant | Compliant |
Application Notes
- LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A)PDF, 101 Kb, Revision: A, File published: Apr 29, 2013
This application note introduces Texas Instrument’s LVDS devices with built-in pre-emphasis andequalization circuits, recommends when it makes sense to employ them with the FPD-Link II SER/DES,shows how to optimally interface them to the SER/DES, and discusses distance gains that may berealized with their signal enhancing functions. - Extending the Reach of a FPD-Link II Interface with Cable Drivers and Equalizers (Rev. A)PDF, 118 Kb, Revision: A, File published: Apr 26, 2013
TI's family of embedded clock LVDS SER/DES (FPD-link II) provides a 2-wire serial interface for displayapplications up to distances of 10 meters.
Model Line
Series: DS99R102 (2)
Manufacturer's Classification
- Semiconductors> Interface> Display & Imaging SerDes> FPD-Link II SerDes