Datasheet Texas Instruments DS99R105
| Manufacturer | Texas Instruments |
| Series | DS99R105 |
3-40MHz DC- Balanced 24-Bit LVDS Serializer
Datasheets
DS99R105/DS99R106 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer datasheet
PDF, 1.0 Mb, Revision: D, File published: Apr 16, 2013
Extract from the document
Status
| DS99R105SQ/NOPB | DS99R105SQX/NOPB | DS99R105VS/NOPB | DS99R105VSX/NOPB | |
|---|---|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes | Yes | No | No |
Packaging
| DS99R105SQ/NOPB | DS99R105SQX/NOPB | DS99R105VS/NOPB | DS99R105VSX/NOPB | |
|---|---|---|---|---|
| N | 1 | 2 | 3 | 4 |
| Pin | 48 | 48 | 48 | 48 |
| Package Type | NJU | NJU | PFB | PFB |
| Industry STD Term | WQFN | WQFN | TQFP | TQFP |
| JEDEC Code | S-PQSO-N | S-PQSO-N | S-PQFP-G | S-PQFP-G |
| Package QTY | 250 | 2500 | 250 | 1000 |
| Carrier | SMALL T&R | LARGE T&R | JEDEC TRAY (10+1) | LARGE T&R |
| Device Marking | DS99R105 | DS99R105 | VS | DS99R105 |
| Width (mm) | 7 | 7 | 7 | 7 |
| Length (mm) | 7 | 7 | 7 | 7 |
| Thickness (mm) | .8 | .8 | 1 | 1 |
| Pitch (mm) | .5 | .5 | .5 | .5 |
| Max Height (mm) | .8 | .8 | 1.2 | 1.2 |
| Mechanical Data | Download | Download | Download | Download |
Parametrics
| Parameters / Models | DS99R105SQ/NOPB | DS99R105SQX/NOPB | DS99R105VS/NOPB | DS99R105VSX/NOPB |
|---|---|---|---|---|
| Approx. Price (US$) | 3.90 | 1ku | |||
| Color Depth, bpp | 18 | 18 | 18 | |
| Color Depth(bpp) | 18 | |||
| Diagnostics | - | - | - | - |
| EMI Reduction | - | - | - | - |
| Function | Serializer | Serializer | Serializer | Serializer |
| Input Compatibility | LVCMOS | LVCMOS | LVCMOS | LVCMOS |
| Operating Temperature Range, C | 0 to 70 | 0 to 70 | 0 to 70 | |
| Operating Temperature Range(C) | 0 to 70 | |||
| Output Compatibility | FPD-Link LVDS | FPD-Link LVDS | FPD-Link LVDS | FPD-Link LVDS |
| Package Group | WQFN | WQFN | TQFP | TQFP |
| Package Size: mm2:W x L, PKG | 48WQFN: 49 mm2: 7 x 7(WQFN) | 48WQFN: 49 mm2: 7 x 7(WQFN) | 48TQFP: 81 mm2: 9 x 9(TQFP) | |
| Package Size: mm2:W x L (PKG) | 48TQFP: 81 mm2: 9 x 9(TQFP) | |||
| Pixel Clock Min, MHz | 3 | 3 | 3 | |
| Pixel Clock Min(MHz) | 3 | |||
| Pixel Clock(Max), MHz | 40 | 40 | 40 | |
| Pixel Clock(Max)(MHz) | 40 | |||
| Rating | Catalog | Catalog | Catalog | Catalog |
| Signal Conditioning | Fixed Pre-Emphasis | Fixed Pre-Emphasis | Fixed Pre-Emphasis | Fixed Pre-Emphasis |
| Special Features | - | - | - | - |
| SupplyVoltage(Volt) | 3.3 | |||
| Total Throughput, Mbps | 960 | 960 | 960 | |
| Total Throughput(Mbps) | 960 |
Eco Plan
| DS99R105SQ/NOPB | DS99R105SQX/NOPB | DS99R105VS/NOPB | DS99R105VSX/NOPB | |
|---|---|---|---|---|
| RoHS | Compliant | Compliant | Compliant | Compliant |
| Pb Free | Yes |
Application Notes
- LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A)PDF, 101 Kb, Revision: A, File published: Apr 29, 2013
This application note introduces Texas Instrument’s LVDS devices with built-in pre-emphasis andequalization circuits, recommends when it makes sense to employ them with the FPD-Link II SER/DES,shows how to optimally interface them to the SER/DES, and discusses distance gains that may berealized with their signal enhancing functions. - Extending the Reach of a FPD-Link II Interface with Cable Drivers and Equalizers (Rev. A)PDF, 118 Kb, Revision: A, File published: Apr 26, 2013
TI's family of embedded clock LVDS SER/DES (FPD-link II) provides a 2-wire serial interface for displayapplications up to distances of 10 meters.
Model Line
Series: DS99R105 (4)
Manufacturer's Classification
- Semiconductors> Interface> Display & Imaging SerDes> FPD-Link II SerDes