Datasheet Texas Instruments SN65LVDS104

Manufacturer	Texas Instruments
Series	SN65LVDS104

1:4 LVDS Clock Fanout Buffer

Datasheets

PDF, 1.2 Mb, Revision: G, File published: Dec 31, 2015

Extract from the document

	SN65LVDS104D	SN65LVDS104DG4	SN65LVDS104DR	SN65LVDS104DRG4	SN65LVDS104PW	SN65LVDS104PWG4	SN65LVDS104PWR	SN65LVDS104PWRG4
Lifecycle Status	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)
Manufacture's Sample Availability	Yes	Yes	Yes	No	No	Yes	No	No

	SN65LVDS104D	SN65LVDS104DG4	SN65LVDS104DR	SN65LVDS104DRG4	SN65LVDS104PW	SN65LVDS104PWG4	SN65LVDS104PWR	SN65LVDS104PWRG4
N	1	2	3	4	5	6	7	8
Pin	16	16	16	16	16	16	16	16
Package Type	D	D	D	D	PW	PW	PW	PW
Industry STD Term	SOIC	SOIC	SOIC	SOIC	TSSOP	TSSOP	TSSOP	TSSOP
JEDEC Code	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G
Package QTY	40	40	2500	2500	90	90	2000	2000
Carrier	TUBE	TUBE	LARGE T&R	LARGE T&R	TUBE	TUBE	LARGE T&R	LARGE T&R
Device Marking	LVDS104	LVDS104	LVDS104	LVDS104	LVDS104	LVDS104	LVDS104	LVDS104
Width (mm)	3.91	3.91	3.91	3.91	4.4	4.4	4.4	4.4
Length (mm)	9.9	9.9	9.9	9.9	5	5	5	5
Thickness (mm)	1.58	1.58	1.58	1.58	1	1	1	1
Pitch (mm)	1.27	1.27	1.27	1.27	.65	.65	.65	.65
Max Height (mm)	1.75	1.75	1.75	1.75	1.2	1.2	1.2	1.2
Mechanical Data	Download	Download	Download	Download	Download	Download	Download	Download

Parameters / Models	SN65LVDS104D	SN65LVDS104DG4	SN65LVDS104DR	SN65LVDS104DRG4	SN65LVDS104PW	SN65LVDS104PWG4	SN65LVDS104PWR	SN65LVDS104PWRG4
Input Frequency(Max), MHz	400	400	400	400	400	400	400	400
Input Level	LVDS	LVDS	LVDS	LVDS	LVDS	LVDS	LVDS	LVDS
Number of Outputs	4	4	4	4	4	4	4	4
Operating Temperature Range, C	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85
Output Frequency(Max), MHz	400	400	400	400	400	400	400	400
Output Level	LVDS	LVDS	LVDS	LVDS	LVDS	LVDS	LVDS	LVDS
Package Group	SOIC	SOIC	SOIC	SOIC	TSSOP	TSSOP	TSSOP	TSSOP
Package Size: mm2:W x L, PKG	16SOIC: 59 mm2: 6 x 9.9(SOIC)	16SOIC: 59 mm2: 6 x 9.9(SOIC)	16SOIC: 59 mm2: 6 x 9.9(SOIC)	16SOIC: 59 mm2: 6 x 9.9(SOIC)	16TSSOP: 32 mm2: 6.4 x 5(TSSOP)	16TSSOP: 32 mm2: 6.4 x 5(TSSOP)	16TSSOP: 32 mm2: 6.4 x 5(TSSOP)	16TSSOP: 32 mm2: 6.4 x 5(TSSOP)
Rating	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog
VCC, V	3.3	3.3	3.3	3.3	3.3	3.3	3.3	3.3
VCC Out, V	3.3	3.3	3.3	3.3	3.3	3.3	3.3	3.3

	SN65LVDS104D	SN65LVDS104DG4	SN65LVDS104DR	SN65LVDS104DRG4	SN65LVDS104PW	SN65LVDS104PWG4	SN65LVDS104PWR	SN65LVDS104PWRG4
RoHS	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant

Download
DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML
PDF, 135 Kb, File published: Feb 19, 2003
Download
AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C)
PDF, 417 Kb, Revision: C, File published: Oct 17, 2007
This report provides a quick reference of ac-coupling techniques for interfacing between different logic levels. The four differential signaling levels found in this reportare low-voltage positive-referenced emitter coupled logic (LVPECL), low-voltage differential signals (LVDS), high-speed transceiver logic (HSTL), and current-modelogic (CML). From these four differential signaling levels, 16

Series: SN65LVDS104 (8)