Datasheet Texas Instruments SN74LVT18512DGGR

ManufacturerTexas Instruments
SeriesSN74LVT18512
Part NumberSN74LVT18512DGGR
Datasheet Texas Instruments SN74LVT18512DGGR

3.3-V ABT Scan Test Devices With 18-Bit Universal Bus Transceivers 64-TSSOP -40 to 85

Datasheets

3.3-V ABT Scan Test Devices With 18-Bit Universal Bus Transceivers datasheet
PDF, 762 Kb, File published: Oct 1, 1997
Extract from the document

Prices

Status

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

Packaging

Pin64
Package TypeDGG
Industry STD TermTSSOP
JEDEC CodeR-PDSO-G
Package QTY2000
CarrierLARGE T&R
Device MarkingLVT18512
Width (mm)6.1
Length (mm)17
Thickness (mm)1.15
Pitch (mm).5
Max Height (mm)1.2
Mechanical DataDownload

Parametrics

Bits18
F @ Nom Voltage(Max)160 Mhz
ICC @ Nom Voltage(Max)24 mA
Operating Temperature Range-40 to 85 C
Output Drive (IOL/IOH)(Max)64/-32 mA
Package GroupTSSOP
Package Size: mm2:W x L64TSSOP: 138 mm2: 8.1 x 17(TSSOP) PKG
RatingCatalog
Technology FamilyLVT
VCC(Max)3.6 V
VCC(Min)2.7 V
Voltage(Nom)3.3 V
tpd @ Nom Voltage(Max)4.9 ns

Eco Plan

RoHSCompliant

Application Notes

  • Programming CPLDs Via the 'LVT8986 LASP
    PDF, 819 Kb, File published: Nov 1, 2005
    This application report summarizes key information required for understanding the 'LVT8986 linking addressable scan ports (LASPs) multidrop addressable IEEE Std 1149.1 (JTAG) test access port (TAP) transceiver. This report includes information about the 'LVT8986 secondary TAPs, bypass and linking shadow protocol, scan-path description languages, serial vector format files, and an example of how to
  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revision: A, File published: Mar 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, File published: Dec 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.

Model Line

Series: SN74LVT18512 (1)
  • SN74LVT18512DGGR

Manufacturer's Classification

  • Semiconductors > Logic > Specialty Logic > Boundary Scan (JTAG) Logic