Datasheet Texas Instruments SN74S112A
| Manufacturer | Texas Instruments |
| Series | SN74S112A |
Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset
Datasheets
Dual J-K Negative-Edge-Triggered Flip-Flops With Preset And Clear datasheet
PDF, 1.3 Mb, File published: Mar 1, 1988
Extract from the document
Prices
Status
| SN74S112AD | SN74S112AN | SN74S112AN3 | |
|---|---|---|---|
| Lifecycle Status | Obsolete (Manufacturer has discontinued the production of the device) | Active (Recommended for new designs) | Obsolete (Manufacturer has discontinued the production of the device) |
| Manufacture's Sample Availability | No | No | No |
Packaging
| SN74S112AD | SN74S112AN | SN74S112AN3 | |
|---|---|---|---|
| N | 1 | 2 | 3 |
| Pin | 16 | 16 | 16 |
| Package Type | D | N | N |
| Industry STD Term | SOIC | PDIP | PDIP |
| JEDEC Code | R-PDSO-G | R-PDIP-T | R-PDIP-T |
| Width (mm) | 3.91 | 6.35 | 6.35 |
| Length (mm) | 9.9 | 19.3 | 19.3 |
| Thickness (mm) | 1.58 | 3.9 | 3.9 |
| Pitch (mm) | 1.27 | 2.54 | 2.54 |
| Max Height (mm) | 1.75 | 5.08 | 5.08 |
| Mechanical Data | Download | Download | Download |
| Package QTY | 25 | ||
| Carrier | TUBE | ||
| Device Marking | SN74S112AN |
Parametrics
| Parameters / Models | SN74S112AD | SN74S112AN | SN74S112AN3 |
|---|---|---|---|
| Approx. Price (US$) | 0.82 | 1ku | 0.82 | 1ku | |
| Bits | 2 | ||
| Bits(#) | 2 | 2 | |
| F @ Nom Voltage(Max), Mhz | 50 | ||
| F @ Nom Voltage(Max)(Mhz) | 50 | 50 | |
| ICC @ Nom Voltage(Max), mA | 6 | ||
| ICC @ Nom Voltage(Max)(mA) | 6 | 6 | |
| Input Type | TTL | TTL | |
| Output Drive (IOL/IOH)(Max), mA | -1/20 | ||
| Output Drive (IOL/IOH)(Max)(mA) | -1/20 | -1/20 | |
| Output Type | TTL | TTL | |
| Package Group | SOIC | PDIP | PDIP |
| Package Size: mm2:W x L, PKG | See datasheet (PDIP) | ||
| Package Size: mm2:W x L (PKG) | See datasheet (PDIP) | See datasheet (PDIP) | |
| Rating | Catalog | Catalog | Catalog |
| Schmitt Trigger | No | No | No |
| Technology Family | S | S | S |
| VCC(Max), V | 5.25 | ||
| VCC(Max)(V) | 5.25 | 5.25 | |
| VCC(Min), V | 4.75 | ||
| VCC(Min)(V) | 4.75 | 4.75 | |
| Voltage(Nom), V | 5 | ||
| Voltage(Nom)(V) | 5 | 5 | |
| tpd @ Nom Voltage(Max), ns | 20 | ||
| tpd @ Nom Voltage(Max)(ns) | 20 | 20 |
Eco Plan
| SN74S112AD | SN74S112AN | SN74S112AN3 | |
|---|---|---|---|
| RoHS | Not Compliant | Compliant | Not Compliant |
| Pb Free | No | No | Yes |
Model Line
Series: SN74S112A (3)
Manufacturer's Classification
- Semiconductors> Logic> Flip-Flop/Latch/Register> J-K Flip-Flop
