Datasheet Texas Instruments TLV2543

ManufacturerTexas Instruments
SeriesTLV2543
Datasheet Texas Instruments TLV2543

12-Bit 66 kSPS ADC Ser. Out, Pgrmable Pwrdn, MSB/LSB First, Built-In Self-Test Mode, 11 Ch.

Datasheets

12-Bit Analog-to-Digital Converters With Serial Control And 11 Analog Inputs datasheet
PDF, 553 Kb, Revision: C, File published: Jun 5, 2000
Extract from the document

Prices

Status

TLV2543CDBTLV2543CDBRTLV2543CDBRG4TLV2543CDWTLV2543CDWG4TLV2543CNTLV2543IDBTLV2543IDBRTLV2543IDBRG4TLV2543IDWTLV2543IDWRTLV2543IN
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityYesNoNoYesYesNoYesNoYesYesYesYes

Packaging

TLV2543CDBTLV2543CDBRTLV2543CDBRG4TLV2543CDWTLV2543CDWG4TLV2543CNTLV2543IDBTLV2543IDBRTLV2543IDBRG4TLV2543IDWTLV2543IDWRTLV2543IN
N123456789101112
Pin202020202020202020202020
Package TypeDBDBDBDWDWNDBDBDBDWDWN
Industry STD TermSSOPSSOPSSOPSOICSOICPDIPSSOPSSOPSSOPSOICSOICPDIP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDIP-TR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDIP-T
Package QTY7020002000252520702000200025200020
CarrierTUBELARGE T&RLARGE T&RTUBETUBETUBETUBELARGE T&RLARGE T&RTUBELARGE T&RTUBE
Device MarkingTV2543TV2543TV2543TLV2543CTLV2543CTLV2543CNTY2543TY2543TY2543TLV2543ITLV2543ITLV2543IN
Width (mm)5.35.35.37.57.56.355.35.35.37.57.56.35
Length (mm)7.27.27.212.812.824.337.27.27.212.812.824.33
Thickness (mm)1.951.951.952.352.354.571.951.951.952.352.354.57
Pitch (mm).65.65.651.271.272.54.65.65.651.271.272.54
Max Height (mm)2222.652.655.082222.652.655.08
Mechanical DataDownloadDownloadDownloadDownloadDownloadDownloadDownloadDownloadDownloadDownloadDownloadDownload

Parametrics

Parameters / ModelsTLV2543CDB
TLV2543CDB
TLV2543CDBR
TLV2543CDBR
TLV2543CDBRG4
TLV2543CDBRG4
TLV2543CDW
TLV2543CDW
TLV2543CDWG4
TLV2543CDWG4
TLV2543CN
TLV2543CN
TLV2543IDB
TLV2543IDB
TLV2543IDBR
TLV2543IDBR
TLV2543IDBRG4
TLV2543IDBRG4
TLV2543IDW
TLV2543IDW
TLV2543IDWR
TLV2543IDWR
TLV2543IN
TLV2543IN
# Input Channels111111111111111111111111
Analog Voltage AVDD(Max), V3.63.63.63.63.63.63.63.63.63.63.63.6
Analog Voltage AVDD(Min), V333333333333
ArchitectureSARSARSARSARSARSARSARSARSARSARSARSAR
Digital Supply(Max), V3.63.63.63.63.63.63.63.63.63.63.63.6
Digital Supply(Min), V333333333333
INL(Max), +/-LSB111111111111
Input Range(Max), V3.63.63.63.63.63.63.63.63.63.63.63.6
Input TypeSingle-EndedSingle-EndedSingle-EndedSingle-EndedSingle-EndedSingle-EndedSingle-EndedSingle-EndedSingle-EndedSingle-EndedSingle-EndedSingle-Ended
Integrated FeaturesN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/A
InterfaceSPISPISPISPISPISPISPISPISPISPISPISPI
Multi-Channel ConfigurationMultiplexedMultiplexedMultiplexedMultiplexedMultiplexedMultiplexedMultiplexedMultiplexedMultiplexedMultiplexedMultiplexedMultiplexed
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Package GroupSSOPSSOPSSOPSOICSOICPDIPSSOPSSOPSSOPSOICSOICPDIP
Package Size: mm2:W x L, PKG20SSOP: 56 mm2: 7.8 x 7.2(SSOP)20SSOP: 56 mm2: 7.8 x 7.2(SSOP)20SSOP: 56 mm2: 7.8 x 7.2(SSOP)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)See datasheet (PDIP)20SSOP: 56 mm2: 7.8 x 7.2(SSOP)20SSOP: 56 mm2: 7.8 x 7.2(SSOP)20SSOP: 56 mm2: 7.8 x 7.2(SSOP)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)See datasheet (PDIP)
Power Consumption(Typ), mW3.33.33.33.33.33.33.33.33.33.33.33.3
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Reference ModeExtExtExtExtExtExtExtExtExtExtExtExt
Resolution, Bits121212121212121212121212
Sample Rate (max), SPS66kSPS66kSPS66kSPS66kSPS66kSPS66kSPS66kSPS66kSPS66kSPS66kSPS66kSPS66kSPS
Sample Rate(Max), MSPS0.0660.0660.0660.0660.0660.0660.0660.0660.0660.0660.0660.066

Eco Plan

TLV2543CDBTLV2543CDBRTLV2543CDBRG4TLV2543CDWTLV2543CDWG4TLV2543CNTLV2543IDBTLV2543IDBRTLV2543IDBRG4TLV2543IDWTLV2543IDWRTLV2543IN
RoHSCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliant
Pb FreeYesYes

Application Notes

  • Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)
    PDF, 227 Kb, Revision: A, File published: Nov 10, 2010
    This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different
  • Determining Minimum Acquisition Times for SAR ADCs, part 2
    PDF, 215 Kb, File published: Mar 17, 2011
    The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to

Model Line

Manufacturer's Classification

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> Precision ADCs (<=10MSPS)
EMS supplier