Datasheet Texas Instruments TMS320C6657

Manufacturer	Texas Instruments
Series	TMS320C6657

Datasheets

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Packaging

Parametrics

Parameters / Models	TMS320C6657CZH	TMS320C6657CZH25	TMS320C6657CZH8	TMS320C6657CZHA	TMS320C6657CZHA25	TMS320C6657GZHA	TMS320C6657SCZH
Applications	Avionics & Defense,Communications,Machine Vision	Avionics & Defense,Communications,Machine Vision	Avionics & Defense,Communications,Machine Vision	Avionics & Defense,Communications,Machine Vision	Avionics & Defense,Communications,Machine Vision	Avionics & Defense,Communications,Machine Vision	Avionics & Defense,Communications,Machine Vision
DRAM	DDR3	DDR3	DDR3	DDR3	DDR3	DDR3	DDR3
DSP	2 C66x	2 C66x	2 C66x	2 C66x	2 C66x	2 C66x	2 C66x
DSP MHz, Max.	1000,1250	1000,1250	1000,1250	1000,1250	1000,1250	1000,1250	1000,1250
EMAC	10/100/1000	10/100/1000	10/100/1000	10/100/1000	10/100/1000	10/100/1000	10/100/1000
GFLOPS	32,40	32,40	32,40	32,40	32,40	32,40	32,40
Hardware Accelerators	VCP2,TCP3d	VCP2,TCP3d	VCP2,TCP3d	VCP2,TCP3d	VCP2,TCP3d	VCP2,TCP3d	VCP2,TCP3d
On-Chip L2 Cache	2048 KB	2048 KB	2048 KB	2048 KB	2048 KB	2048 KB	2048 KB
Operating Temperature Range, C	-40 to 100,0 to 85	-40 to 100,0 to 85	-40 to 100,0 to 85	-40 to 100,0 to 85	-40 to 100,0 to 85	-40 to 100,0 to 85	-40 to 100,0 to 85
Other On-Chip Memory	1024 KB	1024 KB	1024 KB	1024 KB	1024 KB	1024 KB	1024 KB
PCI/PCIe	2 PCIe Gen2	2 PCIe Gen2	2 PCIe Gen2	2 PCIe Gen2	2 PCIe Gen2	2 PCIe Gen2	2 PCIe Gen2
Package Size: mm2:W x L, PKG	See datasheet (FCBGA)	See datasheet (FCBGA)	See datasheet (FCBGA)	See datasheet (FCBGA)	See datasheet (FCBGA)	See datasheet (FCBGA)	See datasheet (FCBGA)
Rating	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog
Serial I/O	Hyperlink,I2C,RapidIO,SPI,TSIP,UART	Hyperlink,I2C,RapidIO,SPI,TSIP,UART	Hyperlink,I2C,RapidIO,SPI,TSIP,UART	Hyperlink,I2C,RapidIO,SPI,TSIP,UART	Hyperlink,I2C,RapidIO,SPI,TSIP,UART	Hyperlink,I2C,RapidIO,SPI,TSIP,UART	Hyperlink,I2C,RapidIO,SPI,TSIP,UART
Serial RapidIO	1 (four lanes)	1 (four lanes)	1 (four lanes)	1 (four lanes)	1 (four lanes)	1 (four lanes)	1 (four lanes)
Total On-Chip Memory, KB	3200	3200	3200	3200	3200	3200	3200

Eco Plan

Application Notes

• Download
  PCI Express (PCIe) Resource Wiki for Keystone Devices (Rev. A)
  PDF, 57 Kb, Revision: A, File published: May 19, 2017
• Download
  Keystone NDK FAQ
  PDF, 54 Kb, File published: Oct 3, 2016
  This document is a collection of frequently asked questions (FAQ) on running the NDK examples on the KeyStoneв„ў family of devices.
• Download
  TI Keystone DSP Hyperlink SerDes IBIS-AMI Models
  PDF, 3.2 Mb, File published: Oct 9, 2014
  This document describes the organization, structure, and proper usage of the TI serializer and deserializer (SerDes) IBIS-AMI models for Keystone DSP Hyperlink interface.
• Download
  TI Keystone DSP PCIe SerDes IBIS-AMI Models
  PDF, 4.8 Mb, File published: Oct 9, 2014
  This document describes the organization, structure, and proper usage of the TI serializer and deserializer (SerDes) IBIS-AMI models for Keystone DSP PCIe interface.
• Download
  SerDes Implementation Guidelines for KeyStone I Devices
  PDF, 590 Kb, File published: Oct 31, 2012
  The goal of KeyStone I SerDes collateral material is to make system implementation easier for the customer by providing the system solution. For these SerDes-based interfaces, it is not assumed that the system designer is familiar with the industry specifications, SerDes technology, or RF/microwave PCB design. However, it is still expected that the PCB design work will be supervised by a knowledge
• Download
  Hardware Design Guide for KeyStone Devices (Rev. C)
  PDF, 1.7 Mb, Revision: C, File published: Sep 15, 2013
• Download
  KeyStone I DDR3 Initialization (Rev. E)
  PDF, 114 Kb, Revision: E, File published: Oct 28, 2016
  The initialization of the DDR3 DRAM controller on KeyStone I DSPs is straightforward as long as the proper steps are followed. However, if some steps are omitted or if some sequence-sensitive steps are implemented in the wrong order, DDR3 operation will be unpredictable.All DDR3 initialization routines must contain the basic register writes to configure the memory controller within the DSP
• Download
  TMS320C66x DSP Generation of Devices (Rev. A)
  PDF, 245 Kb, Revision: A, File published: Apr 25, 2011
• Download
  AN-1281 Bumped Die (Flip Chip) Packages (Rev. A)
  PDF, 2.2 Mb, Revision: A, File published: May 1, 2004
  Application Note 1281 Bumped Die (Flip Chip) Packages
• Download
  SERDES Link Commissioning on KeyStone I and II Devices
  PDF, 138 Kb, File published: Apr 13, 2016
  The serializer-deserializer (SerDes) performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the CPU. This application report explains the SerDes transmit and receive parameters tuning, tools and some debug techniques for TI Keystone I and Keystone II devices.
• Download
  PCIe Use Cases for KeyStone Devices
  PDF, 320 Kb, File published: Dec 13, 2011
• Download
  Clocking Design Guide for KeyStone Devices
  PDF, 1.5 Mb, File published: Nov 9, 2010
• Download
  Optimizing Loops on the C66x DSP
  PDF, 585 Kb, File published: Nov 9, 2010
• Download
  The C6000 Embedded Application Binary Interface Migration Guide (Rev. A)
  PDF, 20 Kb, Revision: A, File published: Nov 10, 2010
  The C6000 compiler tools support a new ELF-based ABI named EABI. Prior to this time, the compiler only supported a single ABI, which is now named COFF ABI. The following compelling best-in-class features are available under the C6000 EABI:GeneralZero-init globals: “int gvar;” gets set to 0 before main runs.Dynamic linking: Add code to a running system.Native ROM
• Download
  DDR3 Design Requirements for KeyStone Devices (Rev. B)
  PDF, 582 Kb, Revision: B, File published: Jun 5, 2014
• Download
  Multicore Programming Guide (Rev. B)
  PDF, 1.8 Mb, Revision: B, File published: Aug 29, 2012
  As application complexity continues to grow, we have reached a limit on increasing performance by merely scaling clock speed. To meet the ever-increasing processing demand, modern System-On-Chip solutions contain multiple processing cores. The dilemma is how to map applications to multicore devices. In this paper, we present a programming methodology for converting applications to run on multicore
• Download
  TI DSP Benchmarking
  PDF, 62 Kb, File published: Jan 13, 2016
  This application report provides benchmarks for the C674x DSP core, the C66x DSP core and the ARMВ®CortexВ®-A15 core. This document also shows how to reproduce these benchmarks on specific hardware platforms.
• Download
  Thermal Design Guide for DSP and ARM Application Processors (Rev. A)
  PDF, 324 Kb, Revision: A, File published: Aug 17, 2016
  This application report has been compiled to provide specific information and considerations regarding thermal design requirements for all DSP and ARM-based single and multi-core processors (collectively referred to as “processors”, “System-on-chip”, or “SoC”). The information contained within this document is intended to provide a minimum level of understanding with regards to the thermal require
• Download
  Plastic Ball Grid Array [PBGA] Application Note (Rev. B)
  PDF, 1.6 Mb, Revision: B, File published: Aug 13, 2015

Model Line

Manufacturer's Classification

• Semiconductors> Processors> Digital Signal Processors> C6000 DSP> C66x DSP