Datasheet Microchip TN2124
| Manufacturer | Microchip |
| Series | TN2124 |
This low threshold, enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and well-proven, silicon-gate manufacturing process
Datasheets
TN2124 Datasheet - N-Channel Enhancement-Mode Vertical DMOS FET
PDF, 723 Kb, Revision: 06-27-2014
Extract from the document
Status
| TN2124K1-G | |
|---|---|
| Lifecycle Status | Production (Appropriate for new designs but newer alternatives may exist) |
Packaging
| TN2124K1-G | |
|---|---|
| N | 1 |
| Package | SOT-23 |
| Pins | 3 |
Parametrics
| Parameters / Models | TN2124K1-G |
|---|---|
| BVdss min, V | 240 |
| CISSmax, pF | 50 |
| Operating Temperature Range, °C | -55 to +150 |
| Rds, on) max | 15 |
| Vgs(th) max, V | 2.0 |
Eco Plan
| TN2124K1-G | |
|---|---|
| RoHS | Compliant |
Model Line
Series: TN2124 (1)