Datasheet Microchip TN5325
| Manufacturer | Microchip |
| Series | TN5325 |
This low threshold, enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and well-proven, silicon-gate manufacturing process
Datasheets
TN5325 N-Channel Enhancement-Mode Vertical DMOS FET Data Sheet
PDF, 865 Kb, Revision: 04-05-2017
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Prices
Status
| TN5325K1-G | TN5325N3-G | TN5325N3-G-P002 | TN5325N8-G | |
|---|---|---|---|---|
| Lifecycle Status | Production (Appropriate for new designs but newer alternatives may exist) | Production (Appropriate for new designs but newer alternatives may exist) | Production (Appropriate for new designs but newer alternatives may exist) | Production (Appropriate for new designs but newer alternatives may exist) |
Packaging
| TN5325K1-G | TN5325N3-G | TN5325N3-G-P002 | TN5325N8-G | |
|---|---|---|---|---|
| N | 1 | 2 | 3 | 4 |
| Package | SOT-23 | TO-92 | TO-92 | SOT-89 |
| Pins | 3 | 3 | 3 | 3 |
Parametrics
| Parameters / Models | TN5325K1-G | TN5325N3-G | TN5325N3-G-P002 | TN5325N8-G |
|---|---|---|---|---|
| BVdss min, V | 250 | 250 | 250 | 250 |
| CISSmax, pF | 110 | 110 | 110 | 110 |
| Operating Temperature Range, °C | -55 to +150 | -55 to +150 | -55 to +150 | -55 to +150 |
| Rds, on) max | 7.0 | 7.0 | 7.0 | 7.0 |
| Vgs(th) max, V | 2.0 | 2.0 | 2.0 | 2.0 |
Eco Plan
| TN5325K1-G | TN5325N3-G | TN5325N3-G-P002 | TN5325N8-G | |
|---|---|---|---|---|
| RoHS | Compliant | Compliant | Compliant | Compliant |
Model Line
Series: TN5325 (4)
