Datasheet Microchip TP5335
| Manufacturer | Microchip |
| Series | TP5335 |
TP5335 is a low threshold enhancement-mode (normally-off) transistor utilizing an advanced vertical DMOS structure and well-proven silicon-gate manufacturing process
Datasheets
TP5335 Datasheet - P-Channel Enhancement-Mode Vertical DMOS FET
PDF, 572 Kb, Revision: 06-27-2014
Extract from the document
Status
| TP5335K1-G | |
|---|---|
| Lifecycle Status | Production (Appropriate for new designs but newer alternatives may exist) |
Packaging
| TP5335K1-G | |
|---|---|
| N | 1 |
| Package | SOT-23 |
| Pins | 3 |
Parametrics
| Parameters / Models | TP5335K1-G |
|---|---|
| BVdss min, V | -350 |
| CISSmax, pF | 110 |
| Operating Temperature Range, °C | -55 to +150 |
| Rds, on) max | 30 |
| Vgs(th) max, V | -2.4 |
Eco Plan
| TP5335K1-G | |
|---|---|
| RoHS | Compliant |
Model Line
Series: TP5335 (1)