**Datasheet**PDF, 82 Kb, Revision: 2014-11-20

CD4063BMS

CMOS 4-Bit Magnitude Comparator December 1992 Features Pinout High Voltage Type (20V Rating) CD4063BMS

TOP VIEW Expansion to 8, 12, 16 . 4N Bits by Cascading Units Medium Speed Operation

-Compares Two 4-Bit Words in 250ns (Typ.) at 10V 100% Tested for Quiescent Current at 20V Standardized Symmetrical Output Characteristics 5V, 10V and 15V Parametric Ratings Maximum Input Current of 1ВµA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC Noise Margin (Full Package Temperature Range)

-1V at VDD = 5V

-2V at VDD = 10V

-2.5V at VDD = 15V Meets All Requirements of JEDEC Tentative Standard

No. 13B, вЂњStandard Specifications for Description of

вЂ?BвЂ™ Series CMOS DevicesвЂќ B3 1 16 VDD (A < B) IN 2 15 A3 (A = B) IN 3 14 B2 (A > B) IN 4 13 A2 (A > B) OUT 5 12 A1 (A = B) OUT 6 11 B1 (A < B) OUT 7 10 A0 VSS 8 9 B0 Functional Diagram

4 Applications WORD A Servo Motor Controls Process Controllers

CASCADING

INPUTS Description

CD4063BMS is a 4-bit magnitude comparator designed for use

in computer and logic applications that require the comparison of

two 4-bit words. This logic circuit determines whether one 4-bit

word (Binary or BCD) is вЂњless thanвЂќ, вЂњequal toвЂќ, or вЂњgreater thanвЂќ a

second 4-bit word. A>B A>B A=B A=B A B) that permit systems designers to

expand the comparator function to 8, 12, 16 . 4N bits. When a

single CD4063BMS is used, the cascading inputs are connected

as follows: (A < B) = low, (A = B) = high, (A > B) = low.

For words longer than 4 bits, CD4063BMS devices may be cascaded by connecting the outputs of the less significant comparator to the corresponding cascading inputs of the more significant

comparator. Cascading inputs (A < B, A = B, and A > B) on the

least significant comparator are connected to a low, a high, and a …