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Datasheet Intersil CD40174BDMSR

Datasheet Intersil CD40174BDMSR

Part NumberCD40174BDMSR

CMOS Hex D-Type Flip-Flop


  • Download » Datasheet PDF, 254 Kb, Revision: 2017-12-22
    CD40174BMS Datasheet
    Docket ↓
    Rev X.00
    Jan 13, 2017 CMOS Hex �D’-Type Flip-Flop Features Pinout High Voltage Type (20V Rating) CD40174BMS
    TOP VIEW 5V, 10V and 15V Parametric Ratings Standardized, Symmetrical Output Characteristics 100% Tested for Quiescent Current at 20V CLEAR 1 16 VDD Q1 2 15 Q6 Maximum Input Current of 1пЃ­A at 18V Over Full Package Temperature Range, 100nA at 18V and +25oC D1 3 14 D6 D2 4 13 D5 Noise Margin (Over full Package Temperature Range):
    -1V at VDD = 5V
    -2V at VDD = 10V
    -2.5V at VDD = 15V Q2 5 12 Q5 D3 6 11 D4 Q3 7 10 Q4
    9 CLOCK VSS 8 Meets All Requirements of JEDEC Tentative Standard
    No. 13A, “Standard Specifications for Description of
    �B’ Series CMOS Devices” Applications Functional Diagram Shift Registers Buffer/Storage Registers D1 2 3
    F/F1 Q1 Pattern Generators
    D2 Description
    CD40174BMS consists of six identical �D’-Type flip-flops
    having independent DATA inputs. The CLOCK and CLEAR
    inputs are common to all six units. Data is transferred to the
    Q outputs on the positive going transition of the clock pulse.
    All six flip-flops are simultaneously reset by a low level on
    the CLEAR input. D3 D4 The CD40174BMS is supplied in these 16 lead outline packages:
    Braze Seal DIP H4T Frit Seal DIP H1E Ceramic Flatpack H6W D5 D5
    CLEAR 4 5
    F/F2 6 7 ...



Package16 Ld SBDIP
Package IndexD16.3


DLA SMD5962-96605
DescriptionCMOS Hex D-Type Flip-Flop
High Dose Rate (HDR) krad(Si)100
Low Dose Rate (ELDRS) krad(Si)ELDRS free
Operating Temperature Range-55 to 125
Qualification LevelQML Class V (space)
SEL (MeV/mg/cm2)75

Eco Plan


Moldel Line

Series: CD40174BMS (2)

Manufacturer's Classification

  • Space & Harsh Environment > Rad Hard Digital > RH Flip-Flops

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