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Datasheet Intersil CD4021BKMSR

Datasheet Intersil CD4021BKMSR

Part NumberCD4021BKMSR

CMOS 8-Stage Static Shift Register


  • Download » Datasheet PDF, 288 Kb, Revision: 2017-12-22
    CD4014BMS, CD4021BMS Datasheet
    Docket ↓
    CD4014BMS, CD4021BMS FN3294
    Rev 0.00
    December 1992 CMOS 8-Stage Static Shift Registers Features Description High Voltage Types (20V Rating) CD4014BMS -Synchronous Parallel or Serial Input/Serial Output Medium Speed Operation 12MHz (Typ.) Clock Rate at
    VDD-VSS = 10V CD4021BMS -Asynchronous Parallel Input or Synchronous
    Serial Input/Serial Output Fully Static Operation CD4014BMS and CD4021BMS series types are 8-stage parallel-or serial-input/serial output registers having common CLOCK
    and PARALLEL/SERIAL CONTROL inputs, a single SERIAL
    data input, and individual parallel “JAM” inputs to each register
    stage. Each register stage is a D-type, master-slave flip-flop. In
    addition to an output from stage 8, “Q” outputs are also available
    from stages 6 and 7. Parallel as well as serial entry is made into
    the register synchronously with the positive clock line transition in
    the CD4014BMS. In the CD4021BMS serial entry is synchronous with the clock but parallel entry is asynchronous. In both
    types, entry is controlled by the PARALLEL/SERIAL CONTROL
    input. When the PARALLEL/SERIAL CONTROL input is low,
    data is serially shifted into the 8-stage register synchronously
    with the positive transition of the clock line. When the PARALLEL/SERIAL CONTROL input is high, data is jammed into the 8stage register via the parallel input lines and synchronous with
    the positive transition of the clock line. In the CD4021BMS, the
    CLOCK input of the internal stage is “forced” when asynchronous parallel entry is made. Register expansion using multiple
    packages is permitted. 8 Master-Slave Flip-Flops Plus Output Buffering and
    Control Gating 100% Tested for Quiescent Current at 20V Maximum Input Current of 1пЃ­A at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC Noise Margin (Full Package Temperature Range) 1V at VDD = 5V 2V at VDD = 10V 2.5V at VDD = 15V Standardized Symmetrical Output Characteristics 5V, 10V and 15V Parametric Ratings Meets All Requirements of JEDEC Tentative Standard
    No. 13B, “Standard Specifications for Description of
    `B' Series CMOS Devices Applications: The CD4014BMS and CD4021BMS are supplied in these 16 ...



Package16 Ld CFP
Package IndexK16.A


DLA SMD5962-96623
DescriptionCMOS 8-Stage Static Shift Register
High Dose Rate (HDR) krad(Si)100
Low Dose Rate (ELDRS) krad(Si)ELDRS free
Operating Temperature Range-55 to 125
Qualification LevelQML Class V (space)
SEL (MeV/mg/cm2)75

Eco Plan


Moldel Line

Series: CD4021BMS (2)

Manufacturer's Classification

  • Space & Harsh Environment > Rad Hard Digital > RH Shift Registers

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