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Datasheet Microchip PL620-88OC

ManufacturerMicrochip
SeriesPL620-88
Part NumberPL620-88OC

The PL620-88 (LVPECL) and PL620-89 (LVDS) are XO ICs specifically designed to work with fundamental or 3rd OT crystals between 19MHz and 65MHz

Datasheets

  • Download » Datasheet, PDF, 350 Kb, 11-09-2015
    PL620-88/-89 - Low Phase Noise XO (9.5-65MHz Output)
    Docket ↓
    PL620-88/-89
    Low Phase Noise XO (9.5-65MHz Output)
    FEATURES п‚ п‚ Crystal input range: 19MHz to 65MHz
    Output range: 9.5MHz – 65MHz
    Very low phase noise and jitter
    Complementary outputs:
    o LVPECL (PL620-88)
    o LVDS (PL620-89)
    Supports 2.5V or 3.3V Power Supply.
    Available in 16 pin TSSOP GREEN/RoHS
    compliant package. VDD 1 16 DNC XIN 2 15 DNC XOUT 3 14 GNDBUF DNC 4 13 QBAR S2^ 5 12 VDDBUF OE 6 11 Q DNC 7 10 GNDBUF GND 8 9 PL620-8x п‚ п‚ п‚ п‚ PIN CONFIGURATION GND TSSOP-16L
    Note: ^ denotes internal pull up OUTPUT ENABLE LOGIC TABLE DESCRIPTION
    The PL620-88 (LVPECL) and PL620-89 (LVDS) are
    XO ICs specifically designed to work with
    fundamental or 3 rd OT crystals between 19MHz and
    65MHz. The selectable divide by two feature extends
    the output range from 9.5MHz to 65MHz. They
    require very low current into the crystal resulting in
    better overall stability. PL620-88
    PL620-89 OE
    0 (Default) State
    Output enabled 1 Tri-state 0 Tri-state 1 (Default) Output enabled OUTPUT FREQUENCY DIVIDE BY
    TWO SELECTOR (S2) BLOCK DIAGRAM O ...

Prices

Status

Lifecycle StatusProduction (Appropriate for new designs but newer alternatives may exist)

Packaging

PackageTSSOP
Pins16

Parametrics

Operating Temperature Range0 to +70 °C
Output Frequency19-65 MHz

Eco Plan

RoHSCompliant

Moldel Line

Series: PL620-88 (2)

Manufacturer's Classification

  • Clock and Timing > Clock Generation > Low Jitter MEMS

Other Names:

PL62088OC, PL620 88OC

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