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Datasheet Microchip SY10H607


The SY10/100H607 are 6-bit, registered, dual supply PECL-to-TTL translators


  • Download » Datasheet PDF, 95 Kb, File published: Nov 7, 2016
    SY10/100H607 - Registered Hex PECL-to-TTL
    Docket ↓
    NOT RECOMMENDED FOR NEW DESIGNS Differential PECL data and clock inputs
    48mA sink, 15mA source TTL outputs
    Single +5V power supply
    Multiple power and ground pins to minimize noise
    Specified within-device skew
    VBB output for single-ended use
    Fully compatible with MC10H/100H607
    Available in 28-pin PLCC package The SY10/100H607 are 6-bit, registered, dual supply
    PECL-to-TTL translators. The devices feature differential
    PECL inputs for both data and clock. The TTL outputs
    feature 48mA sink, 15mA source drive capability for
    driving high fanout loads. The asynchronous master reset
    control is a PECL level input.
    With its differential PECL inputs and TTL outputs, the
    H607 device is ideally suited for the receive function of a
    HPPI bus-type board-to-board interface application. The
    on-chip registers simplify the task of synchronizing the
    data between the two boards.
    The device is available in either ECL standard: the
    10H device is compatible with 10K logic levels, while the
    100H device is compatible with 100K logic levels. BLOCK DIAGRAM PIN NAMES
    Pin 1 OF 6 BITS
    Dn ...


Manufacturer's Classification

  • Clock and Timing > Clock and Data Distribution > Translators

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