Datasheet Microchip SY58627LMG
The SY58627L high-speed, low jitter receive buffer is optimized for backplane and transmission line data-path management applications
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SY58627L Data Sheet
DC-to-6.4Gbps Backplane Receive Buffer with
Four Stage Programmable Equalization
and DC-Offset Control General Description
The SY58627L high-speed, low jitter receive buffer is
optimized for backplane and transmission line data-path
management applications. The SY58627L is capable of
receiving serial data up to 6.4Gbps across up to 36
inches of FR4.
The SY58627L differential input includes Micrelâ€™s
unique, 3-pin input termination architecture that directly
interfaces to any differential signal as small as 100mVpk
(AC-or DC-coupled) without any termination resistor
networks in the signal path. The outputs are 50â„¦
source-terminated CML optimized to drive 400mVpk into
50â„¦ (100â„¦ load across the output pair). The I/O
termination is connected to a dedicated VTT pin for
added bias flexibility.
The SY58627L receiver input provides four levels of
equalization to compensate for degraded signals
resulting from transmission losses. The equalization is
programmed with a three-bit interface.
The SY58627L operates at 3.3V Â±10% supply and is ...
|Lifecycle Status||Production (Appropriate for new designs but newer alternatives may exist)|
|Operating Temperature Range||-40 to +85 °C|
|Output Data Rate||2.5 Max|
|Supply Voltage||3.3V V|
- Clock and Timing > Clock and Data Distribution > Backplane & Cable Management